On 2/15/2024 11:25 PM, Konrad Dybcio wrote:
On 15.02.2024 14:48, Md Sadre Alam wrote:
Add qpic_common.c file which hold all the common
qpic APIs which will be used by both qpic raw nand
driver and qpic spi nand driver.
Co-developed-by: Sricharan Ramabadhran <quic_srichara@xxxxxxxxxxx>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@xxxxxxxxxxx>
Co-developed-by: Varadarajan Narayanan <quic_varada@xxxxxxxxxxx>
Signed-off-by: Varadarajan Narayanan <quic_varada@xxxxxxxxxxx>
Signed-off-by: Md Sadre Alam <quic_mdalam@xxxxxxxxxxx>
---
IIUC this is mostly moving code around?
I do however have some suggestions..
Ok
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/qpic_common.c | 786 +++++++++++++++++
drivers/mtd/nand/raw/qcom_nandc.c | 1226 +-------------------------
include/linux/mtd/nand-qpic-common.h | 488 ++++++++++
4 files changed, 1291 insertions(+), 1210 deletions(-)
create mode 100644 drivers/mtd/nand/qpic_common.c
create mode 100644 include/linux/mtd/nand-qpic-common.h
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 19e1291ac4d5..131707a41293 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -12,3 +12,4 @@ nandcore-$(CONFIG_MTD_NAND_ECC) += ecc.o
nandcore-$(CONFIG_MTD_NAND_ECC_SW_HAMMING) += ecc-sw-hamming.o
nandcore-$(CONFIG_MTD_NAND_ECC_SW_BCH) += ecc-sw-bch.o
nandcore-$(CONFIG_MTD_NAND_ECC_MXIC) += ecc-mxic.o
+obj-y += qpic_common.o
diff --git a/drivers/mtd/nand/qpic_common.c b/drivers/mtd/nand/qpic_common.c
new file mode 100644
index 000000000000..4d74ba888028
--- /dev/null
+++ b/drivers/mtd/nand/qpic_common.c
@@ -0,0 +1,786 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * QPIC Controller common API file.
+ * Copyright (C) 2023 Qualcomm Inc.
+ * Authors: Md sadre Alam <quic_mdalam@xxxxxxxxxxx>
+ * Sricharan R <quic_srichara@xxxxxxxxxxx>
+ * Varadarajan Narayanan <quic_varada@xxxxxxxxxxx>
+ *
+ */
+
+#include <linux/mtd/nand-qpic-common.h>
+
+struct qcom_nand_controller *
+get_qcom_nand_controller(struct nand_chip *chip)
+{
+ return container_of(chip->controller, struct qcom_nand_controller,
+ controller);
+}
+EXPORT_SYMBOL(get_qcom_nand_controller);
#define to_qcom_nand_controller()?
Ok
+
+/*
+ * Helper to prepare DMA descriptors for configuring registers
+ * before reading a NAND page.
+ */
Can you convert these to kerneldoc instead?
Ok
+void config_nand_page_read(struct nand_chip *chip)
+{
+ struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
+
+ write_reg_dma(nandc, NAND_ADDR0, 2, 0);
+ write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
+ if (!nandc->props->qpic_v2)
This is not going to scale going forward.. please include a version
enum instead.
Ok
[...]
+
+int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
+ int reg_off, const void *vaddr, int size,
+ bool flow_control)
+{
+ struct desc_info *desc;
+ struct dma_async_tx_descriptor *dma_desc;
+ struct scatterlist *sgl;
+ struct dma_slave_config slave_conf;
+ struct qcom_adm_peripheral_config periph_conf = {};
+ enum dma_transfer_direction dir_eng;
+ int ret;
Revertse-christmas-tree, please
Ok
+
+ desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+ if (!desc)
+ return -ENOMEM;
+
+ sgl = &desc->adm_sgl;
+
+ sg_init_one(sgl, vaddr, size);
+
+ if (read) {
+ dir_eng = DMA_DEV_TO_MEM;
+ desc->dir = DMA_FROM_DEVICE;
+ } else {
+ dir_eng = DMA_MEM_TO_DEV;
+ desc->dir = DMA_TO_DEVICE;
+ }
+
+ ret = dma_map_sg(nandc->dev, sgl, 1, desc->dir);
+ if (ret == 0) {
if (!ret)
Ok
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ memset(&slave_conf, 0x00, sizeof(slave_conf));
Just zero-initialize it (= { 0 }) at declaration time
Ok
Konrad
Thanks for reviewing , I will fix all the comments in next patch.
Regards,
Alam.
