On 2/20/2024 4:03 AM, Andrew Lunn wrote:
Note it's unable to put the MDIO bus node outside of MAC controller
(i.e. at the same level in the parent bus node). Because we need to
control all clocks and resets in FEMAC driver due to the phy reset
procedure. So the clocks can't be assigned to MDIO bus device, which is
an essential resource for the MDIO bus to work.
What PHY driver is being used? If there a specific PHY driver for this
hardware? Does it implement soft reset?
I'm using generic PHY driver.
It implements IEEE C22 standard. So there is a soft reset in BMCR register.
I'm wondering if you can skip hardware reset of the PHY and only do a
software reset.
There must be someone to deassert the hardware reset control signal for
the PHY. We can't rely on the boot loader to do that. And here even we
choose to skip the hardware reset procedure, the sequence of deasserting
the reset signals is also very important. (i.e. first PHY, then MAC and
MACIF). Opposite to the normal sequence. (we normally first register MAC
driver, and then PHY).
And it might be possible that boot loaders screw all the things up and
we are forced to do the hardware reset procedure in kernel.
Andrew
--
Regards,
Yang Xiwen
