On Sat, Feb 17, 2024 at 2:34 AM Thomas Gleixner <tglx@xxxxxxxxxxxxx> wrote:
>
> On Sat, Jan 27 2024 at 21:47, Anup Patel wrote:
> > We extend the existing APLIC irqchip driver to support MSI-mode for
> > RISC-V platforms having both wired interrupts and MSIs.
>
> We? Just s/We//
Okay, I will update.
>
> > +
> > +static void aplic_msi_irq_unmask(struct irq_data *d)
> > +{
> > + aplic_irq_unmask(d);
> > + irq_chip_unmask_parent(d);
> > +}
> > +
> > +static void aplic_msi_irq_mask(struct irq_data *d)
> > +{
> > + aplic_irq_mask(d);
> > + irq_chip_mask_parent(d);
> > +}
>
> Again asymmetric vs. unmask()
Okay, I will update.
>
> > +static void aplic_msi_irq_eoi(struct irq_data *d)
> > +{
> > + struct aplic_priv *priv = irq_data_get_irq_chip_data(d);
> > + u32 reg_off, reg_mask;
> > +
> > + /*
> > + * EOI handling only required only for level-triggered
> > + * interrupts in APLIC MSI mode.
> > + */
> > +
> > + reg_off = APLIC_CLRIP_BASE + ((d->hwirq / APLIC_IRQBITS_PER_REG) * 4);
> > + reg_mask = BIT(d->hwirq % APLIC_IRQBITS_PER_REG);
> > + switch (irqd_get_trigger_type(d)) {
> > + case IRQ_TYPE_LEVEL_LOW:
> > + if (!(readl(priv->regs + reg_off) & reg_mask))
> > + writel(d->hwirq, priv->regs + APLIC_SETIPNUM_LE);
>
> A comment what this condition is for would be nice.
Okay, I will add a comment about the condition.
Regards,
Anup
