On 18/02/2024 13:02, Yang Xiwen via B4 Relay wrote:
> From: Yang Xiwen <forbidden405@xxxxxxxxxxx>
>
> During boot, the kernel complains:
>
> [ 0.044029] cacheinfo: Unable to detect cache hierarchy for CPU 0
>
> So add L1/L2 cache info to the dts according to the datasheet. (32KiB L1
> i-cache + 32 KiB L1 d-cache + 512 KiB L2 unified cache)
> cpu@3 {
> @@ -52,9 +73,25 @@ cpu@3 {
> device_type = "cpu";
> reg = <0x0 0x3>;
> enable-method = "psci";
> + d-cache-size = <0x8000>; /* 32 KiB */
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + i-cache-size = <0x8000>; /* 32 KiB */
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + next-level-cache = <&L2_0>;
> };
> };
>
> + L2_0: l2-cache0 {
Do you have more than one? If not, then "l2-cache". If yes, then
"l2-cache-0".
Best regards,
Krzysztof
