They are tested on a hi3798mv200 board in fact. Though the 2 SoCs are highly similar and the CPU should be the same. Still, Tested-by are welcomed. The patchset fixes some warnings reported by the kernel during boot. The cache size info is from Processor_Datasheet_v2XX.pdf [1], Section 2.2.1 Master Processor. The cache line size and the set-associative info are from Cortex-A53 Documentation [2]. Dts for other SoCs are also a good reference. >From the doc, we know L1 i-cache is 4-way assoc, L1 d-cache is 2-way assoc and L2 cache is 16-way assoc. Fill the dts props accordingly. Dear maintainers, maybe consider Cc to stable too? [1]: https://github.com/96boards/documentation/blob/master/enterprise/poplar/hardware-docs/Processor_Datasheet_v2XX.pdf [2]: https://developer.arm.com/documentation/ddi0500/j/Level-1-Memory-System Signed-off-by: Yang Xiwen <forbidden405@xxxxxxxxxxx> --- Yang Xiwen (2): arm64: dts: hi3798cv200: Fix the size of GICR arm64: dts: hi3798cv200: add cache info arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 39 +++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) --- base-commit: 8d3dea210042f54b952b481838c1e7dfc4ec751d change-id: 20240218-cache-11c8bf7566c2 Best regards, -- Yang Xiwen <forbidden405@xxxxxxxxxxx>
