Hi Mark,
Acknowledged on anything unmentioned.
> On Feb 13, 2024, at 1:55 PM, Mark Brown <broonie@xxxxxxxxxx> wrote:
>
> On Mon, Feb 12, 2024 at 05:31:11PM +0000, James Ogletree wrote:
>
>> + switch (clk_src) {
>> + case CS40L50_PLL_REFCLK_BCLK:
>> + ret = cs40l50_get_clk_config(codec->sysclk_rate, &clk_cfg);
>> + if (ret)
>> + return ret;
>> + break;
>
> We appear to have a set_sysclk() operation but this is saying the sysclk
> is BCLK? Should the driver be using the bclk_ratio() interface rather
> than set_sysclk(), especially given that the device only appears to
> support either 32.768kHz with no audio or 48kHz and a rather restrictive
> set of multiples of that for the clock?
Yes, I will use the set_bclk_ratio callback in the next version.
>
>> + case CS40L50_PLL_REFCLK_MCLK:
>> + clk_cfg = CS40L50_PLL_CLK_CFG_32768;
>> + break;
>
> MCLK is always 32.768kHz?
When we leave audio mode, we need to go back to a constant 32.768kHz clock.
Best,
James
