The two GPIO banks share a single reset line. Signed-off-by: Théo Lebrun <theo.lebrun@xxxxxxxxxxx> --- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index 0f18ac73620b..5f00d129c057 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -170,6 +170,7 @@ gpio0: gpio@1400000 { #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + resets = <&reset 0 26>; }; gpio1: gpio@1500000 { @@ -183,6 +184,7 @@ gpio1: gpio@1500000 { #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + resets = <&reset 0 26>; }; }; }; -- 2.43.1