On 12/02/2024 17:50, Johan Hovold wrote: > Some Qualcomm SoCs require a minimum performance level for the power > domain so add 'required-opps' to the binding. > > Signed-off-by: Johan Hovold <johan+linaro@xxxxxxxxxx> > --- > Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > index a93ab3b54066..5eda4e72f681 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > @@ -123,6 +123,9 @@ properties: > description: GPIO controlled connection to PERST# signal > maxItems: 1 > > + required-opps: > + maxItems: 1 > + Just letting know that this might conflict with: https://lore.kernel.org/all/20240126-dt-bindings-pci-qcom-split-v3-0-f23cda4d74c0@xxxxxxxxxx/ (I would be happy if my series got applied, so people can base their worn easily on it) Best regards, Krzysztof
