On Sat, 10 Feb 2024 14:45:58 -0600
Adam Ford <aford173@xxxxxxxxx> wrote:
> From: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
>
> This adds the driver for the Samsung HDMI PHY found on the
> i.MX8MP SoC. Based on downstream implementation from
> Sandor Yu <Sandor.yu@xxxxxxx>. According to the TRM, the PHY
> receives parallel data from the link and serializes it. It
> also sets the PLL clock needed for the TX serializer.
>
> Tested-by: Luca Ceresoli <luca.ceresoli@xxxxxxxxxxx> (v2)
> Tested-by: Richard Leitner <richard.leitner@xxxxxxxxxxx> (v2)
> Co-developed-by: Marco Felsch <m.felsch@xxxxxxxxxxxxxx>
> Signed-off-by: Marco Felsch <m.felsch@xxxxxxxxxxxxxx>
> Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
> Tested-by: Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx>
> Tested-by: Frieder Schrempf <frieder.schrempf@xxxxxxxxxx> # Kontron BL
> Tested-by: Luca Ceresoli <luca.ceresoli@xxxxxxxxxxx>
> Signed-off-by: Adam Ford <aford173@xxxxxxxxx>
[...]
> +static int phy_clk_register(struct fsl_samsung_hdmi_phy *phy)
> +{
> + struct device *dev = phy->dev;
> + struct device_node *np = dev->of_node;
> + struct clk_init_data init;
> + const char *parent_name;
> + struct clk *phyclk;
> + int ret;
> +
> + parent_name = __clk_get_name(phy->refclk);
> +
> + init.parent_names = &parent_name;
> + init.num_parents = 1;
> + init.flags = 0;
> + init.name = "hdmi_pclk";
> + init.ops = &phy_clk_ops;
> +
> + phy->hw.init = &init;
> +
> + phyclk = devm_clk_register(dev, &phy->hw);
> + if (IS_ERR(phyclk))
> + return dev_err_probe(dev, PTR_ERR(phyclk),
> + "failed to register clock\n");
> +
> + ret = of_clk_add_provider(np, of_clk_src_simple_get, phyclk);
As per my v8 review, this function is deprecated:
https://elixir.bootlin.com/linux/v6.8-rc4/source/drivers/clk/clk.c#L4881
However:
[Tested using Avnet MSC SM2S-IMX8PLUS SoM on Avnet MSC SM2-MB-EP1]
Tested-by: Luca Ceresoli <luca.ceresoli@xxxxxxxxxxx>
Luca
--
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
