Hi Geert,
Thank you for the review.
On Mon, Feb 12, 2024 at 4:25 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
>
> Hi Prabhakar,
>
> On Mon, Feb 5, 2024 at 3:44 PM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> >
> > All the RZ/G2L and alike SoC's (listed below) have ECCRAM0/1 interrupts
> > supported by the IRQC block, reflect the same in DT binding doc.
> >
> > - R9A07G043U - RZ/G2UL
> > - R9A07G044L/R9A07G044LC - RZ/{G2L,G2LC}
> > - R9A07G054 - RZ/V2L
> > - R9A08G045 - RZ/G3S
> >
> > For the RZ/G3S SoC ("R9A08G045") ECCRAM0/1 interrupts combined into single
> > interrupt so we just use the below to represent them:
> > - ec7tie1-0
> > - ec7tie2-0
> > - ec7tiovf-0
> >
> > Previously, it was assumed that BUS-error and ECCRAM0/1 error interrupts
> > were only supported by RZ/G2UL ("R9A07G043U") and RZ/G3S ("R9A08G045")
> > SoCs. However, in reality, all RZ/G2L and similar SoCs (listed above)
> > support these interrupts. Therefore, mark the 'interrupt-names' property
> > as required for all the SoCs and update the example node in the binding
> > document.
> >
> > Fixes: 96fed779d3d4 ("dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt Controller")
> > Fixes: 1cf0697a24ef ("dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S")
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Thanks for your patch!
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
>
> > --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> > @@ -88,9 +88,15 @@ properties:
> > - description: GPIO interrupt, TINT30
> > - description: GPIO interrupt, TINT31
> > - description: Bus error interrupt
> > + - description: ECCRAM0 1bit error interrupt
> > + - description: ECCRAM0 2bit error interrupt
> > + - description: ECCRAM0 error overflow interrupt
> > + - description: ECCRAM1 1bit error interrupt
> > + - description: ECCRAM1 2bit error interrupt
> > + - description: ECCRAM1 error overflow interrupt
> >
> > interrupt-names:
> > - minItems: 41
> > + minItems: 45
> > items:
> > - const: nmi
> > - const: irq0
> > @@ -134,6 +140,12 @@ properties:
> > - const: tint30
> > - const: tint31
> > - const: bus-err
> > + - const: ec7tie1-0 # For RZ/G3S SoC ("R9A08G045") ECCRAM0/1 interrupts are combined into single interrupt.
> > + - const: ec7tie2-0 # For RZ/G3S SoC ("R9A08G045") ECCRAM0/1 interrupts are combined into single interrupt.
> > + - const: ec7tiovf-0 # For RZ/G3S SoC ("R9A08G045") ECCRAM0/1 interrupts are combined into single interrupt.
>
> These lines are indeed a bit long, and might become longer when newer
> SoCs are introduced.
>
Agreed.
> What about changing the descriptions instead, like
>
> - - description: ECCRAM0 1bit error interrupt
> + - description: ECCRAM0 or combined ECCRAM0/1 1bit error interrupt
>
> ?
>
Agreed, sounds good. I'll just resend this patch fixing this.
Cheers,
Prabhakar
