The SC7180 GCC binding describes clocks which, due to the difference in security model, are not accessible on the RB3gen2 - in the same way seen on QCM6490. Mark these clocks as protected, to allow the board to boot. Signed-off-by: Bjorn Andersson <quic_bjorande@xxxxxxxxxxx> --- I did notice Taniya's patch [1] after writing this patch. I'd prefer to merge this minimal set asap, to make the board boot, unless there's a strong argument for including those other clocks in the protected list. [1] https://lore.kernel.org/linux-arm-msm/20240208062836.19767-6-quic_tdas@xxxxxxxxxxx/ --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 8bb7d13d85f6..97b1586f9f19 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -413,6 +413,24 @@ vreg_bob_3p296: bob { }; }; +&gcc { + protected-clocks = <GCC_CFG_NOC_LPASS_CLK>, + <GCC_EDP_CLKREF_EN>, + <GCC_MSS_CFG_AHB_CLK>, + <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>, + <GCC_MSS_OFFLINE_AXI_CLK>, + <GCC_MSS_Q6SS_BOOT_CLK_SRC>, + <GCC_MSS_Q6_MEMNOC_AXI_CLK>, + <GCC_MSS_SNOC_AXI_CLK>, + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, + <GCC_QSPI_CORE_CLK>, + <GCC_QSPI_CORE_CLK_SRC>, + <GCC_SEC_CTRL_CLK_SRC>, + <GCC_WPSS_AHB_BDG_MST_CLK>, + <GCC_WPSS_AHB_CLK>, + <GCC_WPSS_RSCP_CLK>; +}; + &qupv3_id_0 { status = "okay"; }; --- base-commit: b1d3a0e70c3881d2f8cf6692ccf7c2a4fb2d030d change-id: 20240209-qcm6490-gcc-protected-clocks-ee5fafdb76b3 Best regards, -- Bjorn Andersson <quic_bjorande@xxxxxxxxxxx>
