Anup Patel <apatel@xxxxxxxxxxxxxxxx> writes: > The RISC-V advanced interrupt architecture (AIA) specification > defines a new MSI controller called incoming message signalled > interrupt controller (IMSIC) which manages MSI on per-HART (or > per-CPU) basis. It also supports IPIs as software injected MSIs. > (For more details refer https://github.com/riscv/riscv-aia) > > Let us add an early irqchip driver for RISC-V IMSIC which sets > up the IMSIC state and provide IPIs. > > Signed-off-by: Anup Patel <apatel@xxxxxxxxxxxxxxxx> > --- > drivers/irqchip/Kconfig | 7 + > drivers/irqchip/Makefile | 1 + > drivers/irqchip/irq-riscv-imsic-early.c | 241 +++++++ > drivers/irqchip/irq-riscv-imsic-state.c | 887 ++++++++++++++++++++++++ > drivers/irqchip/irq-riscv-imsic-state.h | 105 +++ > include/linux/irqchip/riscv-imsic.h | 87 +++ > 6 files changed, 1328 insertions(+) > create mode 100644 drivers/irqchip/irq-riscv-imsic-early.c > create mode 100644 drivers/irqchip/irq-riscv-imsic-state.c > create mode 100644 drivers/irqchip/irq-riscv-imsic-state.h > create mode 100644 include/linux/irqchip/riscv-imsic.h > > diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig > index f7149d0f3d45..85f86e31c996 100644 > --- a/drivers/irqchip/Kconfig > +++ b/drivers/irqchip/Kconfig > @@ -546,6 +546,13 @@ config SIFIVE_PLIC > select IRQ_DOMAIN_HIERARCHY > select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP > > +config RISCV_IMSIC > + bool > + depends on RISCV > + select IRQ_DOMAIN_HIERARCHY > + select GENERIC_IRQ_MATRIX_ALLOCATOR > + select GENERIC_MSI_IRQ > + > config EXYNOS_IRQ_COMBINER > bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST > depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST > diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile > index ffd945fe71aa..d714724387ce 100644 > --- a/drivers/irqchip/Makefile > +++ b/drivers/irqchip/Makefile > @@ -95,6 +95,7 @@ obj-$(CONFIG_QCOM_MPM) += irq-qcom-mpm.o > obj-$(CONFIG_CSKY_MPINTC) += irq-csky-mpintc.o > obj-$(CONFIG_CSKY_APB_INTC) += irq-csky-apb-intc.o > obj-$(CONFIG_RISCV_INTC) += irq-riscv-intc.o > +obj-$(CONFIG_RISCV_IMSIC) += irq-riscv-imsic-state.o irq-riscv-imsic-early.o > obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o > obj-$(CONFIG_IMX_IRQSTEER) += irq-imx-irqsteer.o > obj-$(CONFIG_IMX_INTMUX) += irq-imx-intmux.o > diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchip/irq-riscv-imsic-early.c > new file mode 100644 > index 000000000000..3557e32a713c > --- /dev/null > +++ b/drivers/irqchip/irq-riscv-imsic-early.c > @@ -0,0 +1,241 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2021 Western Digital Corporation or its affiliates. > + * Copyright (C) 2022 Ventana Micro Systems Inc. > + */ > + > +#define pr_fmt(fmt) "riscv-imsic: " fmt > +#include <linux/cpu.h> > +#include <linux/interrupt.h> > +#include <linux/io.h> > +#include <linux/irq.h> > +#include <linux/irqchip.h> > +#include <linux/irqchip/chained_irq.h> > +#include <linux/module.h> > +#include <linux/spinlock.h> > +#include <linux/smp.h> > + > +#include "irq-riscv-imsic-state.h" > + > +static int imsic_parent_irq; > + > +#ifdef CONFIG_SMP > +static irqreturn_t imsic_local_sync_handler(int irq, void *data) > +{ > + imsic_local_sync(); > + return IRQ_HANDLED; > +} > + > +static void imsic_ipi_send(unsigned int cpu) > +{ > + struct imsic_local_config *local = > + per_cpu_ptr(imsic->global.local, cpu); > + > + writel_relaxed(IMSIC_IPI_ID, local->msi_va); > +} > + > +static void imsic_ipi_starting_cpu(void) > +{ > + /* Enable IPIs for current CPU. */ > + __imsic_id_set_enable(IMSIC_IPI_ID); > + > + /* Enable virtual IPI used for IMSIC ID synchronization */ > + enable_percpu_irq(imsic->ipi_virq, 0); > +} > + > +static void imsic_ipi_dying_cpu(void) > +{ > + /* > + * Disable virtual IPI used for IMSIC ID synchronization so > + * that we don't receive ID synchronization requests. > + */ > + disable_percpu_irq(imsic->ipi_virq); > +} > + > +static int __init imsic_ipi_domain_init(void) > +{ > + int virq; > + > + /* Create IMSIC IPI multiplexing */ > + virq = ipi_mux_create(IMSIC_NR_IPI, imsic_ipi_send); > + if (virq <= 0) > + return (virq < 0) ? virq : -ENOMEM; > + imsic->ipi_virq = virq; > + > + /* First vIRQ is used for IMSIC ID synchronization */ > + virq = request_percpu_irq(imsic->ipi_virq, imsic_local_sync_handler, > + "riscv-imsic-lsync", imsic->global.local); There's a lot of boilerplate for the local-sync IPI. Any reason not to use what the kernel provides out-of-the-box: int smp_call_function_single(int cpuid, smp_call_func_t func, void *info, int wait); e.g. smp_call_function_single(target_cpu, imsic_local_sync_with_new_signature, NULL, 0); Björn