On 5.02.2024 17:31, Krzysztof Kozlowski wrote: > Each group of MSI interrupts is mapped to the separate host interrupt. > Describe each of interrupts in the device tree for PCIe hosts. This > also corrects PCIe1 and PCIe2 first MSI interrupt. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> > > --- > > Not tested on HW. Booted sc8180x-primus, NVMe is still accessible Tested-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx> Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx> Konrad
