On Sat, 03 Feb 2024 10:52:43 -0600, Adam Ford wrote: > Per guidance from the NXP downstream kernel, if the clock is > disabled before HDMI/LCDIF probe, LCDIF will not get pixel > clock from HDMI PHY and throw an error: > > [CRTC:39:crtc-2] vblank wait timed out > WARNING: CPU: 2 PID: 9 at drivers/gpu/drm/drm_atomic_helper.c: > 1634 drm_atomic_helper_wait_for_vblanks.part.0+0x23c/0x260 > > Fix this by adding the fdcc clock to the hdmi_blk_ctrl. This > should be safe, since neither this power domain nor the dependent > HDMI and LCDIF drivers been enabled or added to the SoC device > tree yet. > > According to Sandor Yu from NXP, "the FDCC clock is not for HDMITX > in desgin, but it is part of HDMI domain that needed by HDMITX. > So I think it is reasonable added it to the power domain driver." > > The driver also supports two power domains which are missing from the binding > that also fix an issue with resuming from suspend. > > Signed-off-by: Adam Ford <aford173@xxxxxxxxx> > --- > V2: Update commit message to both show error and give a bit more > background. > Add missing power domains hdcp and hdrv as pointed out by Marek Vasut > --- > .../soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml | 22 ++++++++++++------- > 1 file changed, 14 insertions(+), 8 deletions(-) > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
