On Thu, Feb 01, 2024 at 09:52:20PM +0000, Daniel Golle wrote: > Add bindings for the MediaTek XFI T-PHY Ethernet SerDes PHY found in the > MediaTek MT7988 SoC which can operate at various interfaces modes: This is v4 unless I'm confused[1]. Where's the revision history? Rob [1] https://lore.kernel.org/all/b875f693f6d4367a610a12ef324584f3bf3a1c1c.1702352117.git.daniel@xxxxxxxxxxxxxx/ > > via USXGMII PCS: > * USXGMII > * 10GBase-R > * 5GBase-R > > via LynxI SGMII PCS: > * 2500Base-X > * 1000Base-X > * Cisco SGMII (MAC side) > > Signed-off-by: Daniel Golle <daniel@xxxxxxxxxxxxxx> > --- > .../bindings/phy/mediatek,xfi-tphy.yaml | 80 +++++++++++++++++++ > 1 file changed, 80 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml > new file mode 100644 > index 0000000000000..e897118dcf7e6 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml > @@ -0,0 +1,80 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/mediatek,xfi-tphy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek XFI T-PHY > + > +maintainers: > + - Daniel Golle <daniel@xxxxxxxxxxxxxx> > + > +description: > + The MediaTek XFI SerDes T-PHY provides the physical SerDes lanes > + used by the (10G/5G) USXGMII PCS and (1G/2.5G) LynxI PCS found in > + MediaTek's 10G-capabale SoCs. > + > +properties: > + $nodename: > + pattern: "^phy@[0-9a-f]+$" > + > + compatible: > + const: mediatek,mt7988-xfi-tphy > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: XFI PHY clock > + - description: XFI register clock > + > + clock-names: > + items: > + - const: xfipll > + - const: topxtal > + > + resets: > + items: > + - description: PEXTP reset What is PEXTP?
