On Wed, 31 Jan 2024 17:06:45 +0000, Dragan Cvetic wrote: > Convert AMD (Xilinx) sd-fec bindings to yaml format, so it can validate > dt-entries as well as any future additions to yaml. > Change in clocks is due to IP is itself configurable and > only the first two clocks are in all combinations. The last > 6 clocks can be present in some of them. It means order is > not really fixed and any combination is possible. > Interrupt may or may not be present. > The documentation for sd-fec bindings is now YAML, so update the > MAINTAINERS file. > Update the link to the new yaml file in xilinx_sdfec.rst. > > Signed-off-by: Dragan Cvetic <dragan.cvetic@xxxxxxx> > --- > Changes in v2: > --- > Drop clocks description. > Use "contains:" with enum for optional clock-names and update > comment explaining diference from the original DT binding file. > Remove trailing full stops. > Add more details in sdfec-code description. > Set sdfec-code to "string" not "string-array" > --- > Changes in v3: > Fix a mistake in example, set interrupt type to 0. > --- > Changes in v4: > Set interrupt type to high level sensitive. > Remove '|' from descriptions, no need to preserve format. > Remove not needed empty line. > --- > Changes in v5: > Apply allOf to clock-names and put permanent clock items > inside enum. > --- > .../devicetree/bindings/misc/xlnx,sd-fec.txt | 58 -------- > .../devicetree/bindings/misc/xlnx,sd-fec.yaml | 140 ++++++++++++++++++ > Documentation/misc-devices/xilinx_sdfec.rst | 2 +- > MAINTAINERS | 2 +- > 4 files changed, 142 insertions(+), 60 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/misc/xlnx,sd-fec.txt > create mode 100644 Documentation/devicetree/bindings/misc/xlnx,sd-fec.yaml > Applied, thanks!
