On Thu, Feb 1, 2024 at 9:49 AM Uwe Kleine-König <u.kleine-koenig@xxxxxxxxxxxxxx> wrote:
>
> hello Aleksandr,
>
> On Wed, Jan 31, 2024 at 03:59:15PM +0300, Aleksandr Shubin wrote:
> > +#include <linux/bitfield.h>
> > +#include <linux/clk.h>
> > +#include <linux/err.h>
> > +#include <linux/io.h>
> > +#include <linux/module.h>
> > +#include <linux/of_device.h>
>
> Some time ago there was some effort by Rob Herring to detangle the
> headers platform_device.h, of_device.h and of.h. See for example commit
> 87e51b76c9db8c29cde573af0faf5a3e13e23960. I think you should use
> linux/of.h instead of linux/of_device.h.
>
> > +#include <linux/platform_device.h>
> > +#include <linux/pwm.h>
> > +#include <linux/reset.h>
> > +
> > +#define SUN20I_PWM_CLK_CFG(chan) (0x20 + (((chan) >> 1) * 0x4))
> > +#define SUN20I_PWM_CLK_CFG_SRC GENMASK(8, 7)
> > +#define SUN20I_PWM_CLK_CFG_DIV_M GENMASK(3, 0)
> > +#define SUN20I_PWM_CLK_DIV_M_MAX 8
>
> SUN20I_PWM_CLK_CFG_DIV_M_MAX?
>
Yes. The manuals mark [0x9, 0xF] as reserved
> > +#define SUN20I_PWM_CLK_GATE 0x40
> > +#define SUN20I_PWM_CLK_GATE_BYPASS(chan) BIT((chan) + 16)
> > +#define SUN20I_PWM_CLK_GATE_GATING(chan) BIT(chan)
> > +
> > +#define SUN20I_PWM_ENABLE 0x80
> > +#define SUN20I_PWM_ENABLE_EN(chan) BIT(chan)
> > +
> > +#define SUN20I_PWM_CTL(chan) (0x100 + (chan) * 0x20)
> > +#define SUN20I_PWM_CTL_ACT_STA BIT(8)
> > +#define UN20I_PWM_CTL_PRESCAL_K GENMASK(7, 0)
> > +#define SUN20I_PWM_CTL_PRESCAL_K_MAX 0xff
>
> This matches the theoretical maximum for GENMASK(7,0), so you could make
> use of field_max(SUN20I_PWM_CTL_PRESCAL_K) here.
>
> > +#define SUN20I_PWM_PERIOD(chan) (0x104 + (chan) * 0x20)
> > +#define SUN20I_PWM_PERIOD_ENTIRE_CYCLE GENMASK(31, 16)
> > +#define SUN20I_PWM_PERIOD_ACT_CYCLE GENMASK(15, 0)
> > +
> > +#define SUN20I_PWM_PCNTR_SIZE BIT(16)
> > +
> > +/**
> > + * SUN20I_PWM_MAGIC is used to quickly compute the values of the clock dividers
> > + * div_m (SUN20I_PWM_CLK_CFG_DIV_M) & prescale_k (SUN20I_PWM_CTL_PRESCAL_K)
> > + * without using a loop. These dividers limit the # of cycles in a period
> > + * to SUN20I_PWM_PCNTR_SIZE by applying a scaling factor of
> > + * 1/(div_m * (prescale_k + 1)) to the clock source.
> > + *
> > + * SUN20I_PWM_MAGIC is derived by solving for div_m and prescale_k
> > + * such that for a given requested period,
> > + *
> > + * i) div_m is minimized for any prescale_k ≤ SUN20I_PWM_CTL_PRESCAL_K_MAX,
> > + * ii) prescale_k is minimized.
> > + *
> > + * The derivation proceeds as follows, with val = # of cycles for reqested
>
> s/reqested/requested/
Nice catch.
> > + * period:
> > + *
> > + * for a given value of div_m we want the smallest prescale_k such that
> > + *
> > + * (val >> div_m) // (prescale_k + 1) ≤ 65536 (SUN20I_PWM_PCNTR_SIZE)
> > + *
> > + * This is equivalent to:
> > + *
> > + * (val >> div_m) ≤ 65536 * (prescale_k + 1) + prescale_k
> > + * ⟺ (val >> div_m) ≤ 65537 * prescale_k + 65536
> > + * ⟺ (val >> div_m) - 65536 ≤ 65537 * prescale_k
> > + * ⟺ ((val >> div_m) - 65536) / 65537 ≤ prescale_k
> > + *
> > + * As prescale_k is integer, this becomes
> > + *
> > + * ((val >> div_m) - 65536) // 65537 ≤ prescale_k
> > + *
> > + * And is minimized at
> > + *
> > + * ((val >> div_m) - 65536) // 65537
> > + *
> > + * Now we pick the smallest div_m that satifies prescale_k ≤ 255
> > + * (i.e SUN20I_PWM_CTL_PRESCAL_K_MAX),
> > + *
> > + * ((val >> div_m) - 65536) // 65537 ≤ 255
> > + * ⟺ (val >> div_m) - 65536 ≤ 255 * 65537 + 65536
> > + * ⟺ val >> div_m ≤ 255 * 65537 + 2 * 65536
> > + * ⟺ val >> div_m < (255 * 65537 + 2 * 65536 + 1)
> > + * ⟺ div_m = fls((val) / (255 * 65537 + 2 * 65536 + 1))
> > + *
> > + * Suggested by Uwe Kleine-König
>
> Good man, I assume this is all sane then :-)
Credit should be given where it is due :-)
> > + */
> > +#define SUN20I_PWM_MAGIC (255 * 65537 + 2 * 65536 + 1)
> > +
> > +struct sun20i_pwm_chip {
> > + struct clk *clk_bus, *clk_hosc, *clk_apb0;
> > + struct reset_control *rst;
> > + struct pwm_chip chip;
> > + void __iomem *base;
> > + /* Mutex to protect pwm apply state */
> > + struct mutex mutex;
> > +};
> > +
> > +static inline struct sun20i_pwm_chip *to_sun20i_pwm_chip(struct pwm_chip *chip)
> > +{
> > + return container_of(chip, struct sun20i_pwm_chip, chip);
> > +}
> > +
> > +static inline u32 sun20i_pwm_readl(struct sun20i_pwm_chip *chip,
> > + unsigned long offset)
> > +{
> > + return readl(chip->base + offset);
> > +}
> > +
> > +static inline void sun20i_pwm_writel(struct sun20i_pwm_chip *chip,
> > + u32 val, unsigned long offset)
> > +{
> > + writel(val, chip->base + offset);
> > +}
> > +
> > +static int sun20i_pwm_get_state(struct pwm_chip *chip,
> > + struct pwm_device *pwm,
> > + struct pwm_state *state)
> > +{
> > + struct sun20i_pwm_chip *sun20i_chip = to_sun20i_pwm_chip(chip);
> > + u16 ent_cycle, act_cycle, prescale_k;
> > + u64 clk_rate, tmp;
> > + u8 div_m;
> > + u32 val;
> > +
> > + mutex_lock(&sun20i_chip->mutex);
> > +
> > + val = sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_CLK_CFG(pwm->hwpwm));
> > + div_m = FIELD_GET(SUN20I_PWM_CLK_CFG_DIV_M, val);
> > + if (div_m > SUN20I_PWM_CLK_DIV_M_MAX)
> > + div_m = SUN20I_PWM_CLK_DIV_M_MAX;
> > +
> > + if (FIELD_GET(SUN20I_PWM_CLK_CFG_SRC, val) == 0)
> > + clk_rate = clk_get_rate(sun20i_chip->clk_hosc);
> > + else
> > + clk_rate = clk_get_rate(sun20i_chip->clk_apb0);
> > +
> > + val = sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_CTL(pwm->hwpwm));
> > + state->polarity = (SUN20I_PWM_CTL_ACT_STA & val) ?
> > + PWM_POLARITY_NORMAL : PWM_POLARITY_INVERSED;
> > +
> > + prescale_k = FIELD_GET(SUN20I_PWM_CTL_PRESCAL_K, val) + 1;
> > +
> > + val = sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_ENABLE);
> > + state->enabled = (SUN20I_PWM_ENABLE_EN(pwm->hwpwm) & val) ? true : false;
> > +
> > + val = sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_PERIOD(pwm->hwpwm));
> > +
> > + mutex_unlock(&sun20i_chip->mutex);
> > +
> > + act_cycle = FIELD_GET(SUN20I_PWM_PERIOD_ACT_CYCLE, val);
> > + ent_cycle = FIELD_GET(SUN20I_PWM_PERIOD_ENTIRE_CYCLE, val);
> > +
> > + /*
> > + * The duration of the active phase should not be longer
> > + * than the duration of the period
> > + */
> > + if (act_cycle > ent_cycle)
> > + act_cycle = ent_cycle;
> > +
> > + tmp = ((u64)(act_cycle) * prescale_k << div_m) * NSEC_PER_SEC;
> > + state->duty_cycle = DIV_ROUND_UP_ULL(tmp, clk_rate);
> > + tmp = ((u64)(ent_cycle) * prescale_k << div_m) * NSEC_PER_SEC;
> > + state->period = DIV_ROUND_UP_ULL(tmp, clk_rate);
>
> Please add a comment above this block that justifies assuming that the
> multiplication doesn't overflow. Something like:
>
> We have act_cycle <= ent_cycle <= 0xffff, prescale_k <= 0x100,
> div_m <= 8. So the multiplication fits into an u64 without
> overflow.
>
> > +
> > + return 0;
> > +}
> > +
> > +static int sun20i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> > + const struct pwm_state *state)
> > +{
> > +...
> > +}
>
> I didn't recheck all the logic in .apply in detail and will assume it is
> sane for this round.
Please do recheck. This thing is already on v8 and we want to make sure
everyone is happy with v9.
> > +static const struct pwm_ops sun20i_pwm_ops = {
> > + .apply = sun20i_pwm_apply,
> > + .get_state = sun20i_pwm_get_state,
> > +};
> > +
> > +static const struct of_device_id sun20i_pwm_dt_ids[] = {
> > + { .compatible = "allwinner,sun20i-d1-pwm" },
> > + { },
> > +};
> > +MODULE_DEVICE_TABLE(of, sun20i_pwm_dt_ids);
> > +
> > +static int sun20i_pwm_probe(struct platform_device *pdev)
> > +{
> > + struct sun20i_pwm_chip *sun20i_chip;
> > + int ret;
> > +
> > + sun20i_chip = devm_kzalloc(&pdev->dev, sizeof(*sun20i_chip), GFP_KERNEL);
> > + if (!sun20i_chip)
> > + return -ENOMEM;
> > +
> > + sun20i_chip->base = devm_platform_ioremap_resource(pdev, 0);
> > + if (IS_ERR(sun20i_chip->base))
> > + return PTR_ERR(sun20i_chip->base);
> > +
> > + sun20i_chip->clk_bus = devm_clk_get_enabled(&pdev->dev, "bus");
> > + if (IS_ERR(sun20i_chip->clk_bus))
> > + return dev_err_probe(&pdev->dev, PTR_ERR(sun20i_chip->clk_bus),
> > + "failed to get bus clock\n");
> > +
> > + sun20i_chip->clk_hosc = devm_clk_get_enabled(&pdev->dev, "hosc");
> > + if (IS_ERR(sun20i_chip->clk_hosc))
> > + return dev_err_probe(&pdev->dev, PTR_ERR(sun20i_chip->clk_hosc),
> > + "failed to get hosc clock\n");
> > +
> > + sun20i_chip->clk_apb0 = devm_clk_get_enabled(&pdev->dev, "apb0");
> > + if (IS_ERR(sun20i_chip->clk_apb0))
> > + return dev_err_probe(&pdev->dev, PTR_ERR(sun20i_chip->clk_apb0),
> > + "failed to get apb0 clock\n");
> > +
> > + sun20i_chip->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
> > + if (IS_ERR(sun20i_chip->rst))
> > + return dev_err_probe(&pdev->dev, PTR_ERR(sun20i_chip->rst),
> > + "failed to get bus reset\n");
> > +
> > + ret = of_property_read_u32(pdev->dev.of_node, "allwinner,pwm-channels",
> > + &sun20i_chip->chip.npwm);
> > + if (ret)
> > + sun20i_chip->chip.npwm = 8;
> > +
> > + if (sun20i_chip->chip.npwm > 16)
> > + sun20i_chip->chip.npwm = 16;
>
> Is it worth to emit an error message here? Something like:
>
> Limiting number of PWM lines from %u to 16
>
> Best regards
> Uwe
>
> --
> Pengutronix e.K. | Uwe Kleine-König |
> Industrial Linux Solutions | https://www.pengutronix.de/ |
Brandon.
