Linus, On Fri, 02 Feb 2024, Karel Balej wrote: > Lee Jones, 2024-02-02T12:45:50+00:00: > > On Thu, 01 Feb 2024, Karel Balej wrote: > > > > > Lee Jones, 2024-01-31T11:03:11+00:00: > > > > On Sun, 28 Jan 2024, Karel Balej wrote: > > > > > > > + /* GPIO1: DVC, GPIO0: input */ > > > > > > > + REG_SEQ0(PM88X_REG_GPIO_CTRL1, 0x40), Do we have a precedent for drivers setting up their own pins like this? > > > > > > Shouldn't you set these up using Pintrl? > > > > > > > > > > You mean to add a new MFD cell for the pins and write the respective > > > > > driver? The downstream implementation has no such thing so I'm not sure > > > > > if I would be able to do that from scratch. > > > > > > > > This is not a Pinctrl driver. > > > > > > > > Isn't there a generic API you can use? > > > > > > I'm sorry, I don't think I understand what you mean. > > > > Perhaps I misunderstand the code. It looks like this regmap patch hack > > is configuring pins and a bunch of other things. Would that be a > > correct assessment? > > Yes, that sounds correct. > > > If so, where do we draw the line here? Do we accept a 1000 line driver > > which configures a large SoC with a bunch of bespoke register writes? > > I understand, I just don't know what you mean by "a generic API". I'm > also not clear on whether what you have in mind is simply adding a > dedicated driver for the pins as a new subdevice of this MFD. -- Lee Jones [李琼斯]
