On 04/01/2024 15:30, Swapnil Jakhade wrote: > Torrent PHY can have separate input reference clocks for PLL0 and PLL1. > Add support for dual reference clock multilink configurations. > > Add register sequences for PCIe(100MHz) + USXGMII(156.25MHz) multilink > configuration. PCIe uses PLL0 and USXGMII uses PLL1. > > Signed-off-by: Swapnil Jakhade <sjakhade@xxxxxxxxxxx> Reviewed-by: Roger Quadros <rogerq@xxxxxxxxxx>
