The "apps_smmu" on the Qualcomm sdm845 platform is an implementation of the SMMU-500, that consists of a single TCU (Translation Control Unit) and multiple TBUs (Translation Buffer Units). The TCU is already being described in the ARM SMMU schema and now we have also a common schema for TBUs. The TBUs on Qualcomm platforms have some additional hardware resources that need to be described in the schema. Create a vendor-specific TBU schema to include all the needed resources like clocks, power domains and interconnects. Signed-off-by: Georgi Djakov <quic_c_gdjako@xxxxxxxxxxx> --- .../devicetree/bindings/iommu/arm,smmu.yaml | 10 +++ .../bindings/iommu/qcom,qsmmuv500-tbu.yaml | 71 +++++++++++++++++++ 2 files changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index ba3237023b39..537e6a2fc02b 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -326,6 +326,16 @@ allOf: through the TCU's programming interface. - description: bus clock required for the smmu ptw + - if: + properties: + compatible: + contains: + const: qcom,sdm845-smmu-500 + then: + patternProperties: + "^tbu@[0-9a-f]+$": + $ref: qcom,qsmmuv500-tbu.yaml# + - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml b/Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml new file mode 100644 index 000000000000..0e86e1c42133 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu/qcom,qsmmuv500-tbu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm TBU (Translation Buffer Unit) + +maintainers: + - Georgi Djakov <quic_c_gdjako@xxxxxxxxxxx> + +description: + The Qualcomm SMMU500 implementation consists of TCU and TBU. The TBU contains + a Translation Lookaside Buffer (TLB) that caches page tables. TBUs provides + debug features to trace and trigger debug transactions. There are multiple TBU + instances with each client core. + +allOf: + - $ref: tbu-common.yaml# + +properties: + compatible: + const: qcom,qsmmuv500-tbu + + clocks: + maxItems: 1 + + interconnects: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - stream-id-range + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + #include <dt-bindings/interconnect/qcom,icc.h> + #include <dt-bindings/interconnect/qcom,sdm845.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + iommu@15000000 { + compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; + reg = <0x15000000 0x80000>; + ranges = <0 0 0 0 0xffffffff>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <2>; + #size-cells = <2>; + + tbu@150e1000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x0 0x150e1000 0x0 0x1000>; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC>; + stream-id-range = <0x1c00 0x400>; + }; + }; +...