On Wed, Jan 31, 2024 at 01:58:08PM +0800, Xu Yang wrote: > i.MX95 has a DDR PMU which is almostly same as i.MX93, it now supports > read beat and write beat filter capabilities. This will add support for > i.MX95 and enhance the driver to support specific filter handling for it. > > Usage: > > For read beat: > ~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt2,counter=3,axi_mask=ID_MASK,axi_id=ID/ > ~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt1,counter=4,axi_mask=ID_MASK,axi_id=ID/ > ~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt0,counter=5,axi_mask=ID_MASK,axi_id=ID/ > eg: For edma2: perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt0,counter=5,axi_mask=0x00f,axi_id=0x00c/ > > For write beat: > ~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_wr_beat_filt,counter=2,axi_mask=ID_MASK,axi_id=ID/ > eg: For edma2: perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_wr_beat_filt,counter=2,axi_mask=0x00f,axi_id=0x00c/ > > Signed-off-by: Xu Yang <xu.yang_2@xxxxxxx> Reviewed-by: Frank Li <Frank.Li@xxxxxxx> > > --- > Changes in v2: > - put soc spefific axi filter events to drvdata according > to franks suggestions. > - adjust pmcfg axi_id and axi_mask config > Changes in v3: > - no changes > Changes in v4: > - only contain imx95 parts > --- > drivers/perf/fsl_imx9_ddr_perf.c | 86 +++++++++++++++++++++++++++++++- > 1 file changed, 84 insertions(+), 2 deletions(-) > > diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c > index b1a58e9e1617..85aaaef7212f 100644 > --- a/drivers/perf/fsl_imx9_ddr_perf.c > +++ b/drivers/perf/fsl_imx9_ddr_perf.c > @@ -17,9 +17,19 @@ > #define MX93_PMCFG1_RD_BT_FILT_EN BIT(29) > #define MX93_PMCFG1_ID_MASK GENMASK(17, 0) > > +#define MX95_PMCFG1_WR_BEAT_FILT_EN BIT(31) > +#define MX95_PMCFG1_RD_BEAT_FILT_EN BIT(30) > + > #define PMCFG2 0x04 > #define MX93_PMCFG2_ID GENMASK(17, 0) > > +#define PMCFG3 0x08 > +#define PMCFG4 0x0C > +#define PMCFG5 0x10 > +#define PMCFG6 0x14 > +#define MX95_PMCFG_ID_MASK GENMASK(9, 0) > +#define MX95_PMCFG_ID GENMASK(25, 16) > + > /* Global control register affects all counters and takes priority over local control registers */ > #define PMGC0 0x40 > /* Global control register bits */ > @@ -240,6 +250,18 @@ static struct attribute *imx93_ddr_perf_events_attrs[] = { > NULL, > }; > > +static struct attribute *imx95_ddr_perf_events_attrs[] = { > + /* counter2 specific events */ > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_beat_filt, 73), > + /* counter3 specific events */ > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt2, 73), > + /* counter4 specific events */ > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt1, 73), > + /* counter5 specific events */ > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt0, 73), > + NULL, > +}; > + > PMU_FORMAT_ATTR(event, "config:0-7"); > PMU_FORMAT_ATTR(counter, "config:8-15"); > PMU_FORMAT_ATTR(axi_id, "config1:0-17"); > @@ -271,8 +293,14 @@ static const struct imx_ddr_devtype_data imx93_devtype_data = { > .attrs = imx93_ddr_perf_events_attrs, > }; > > +static const struct imx_ddr_devtype_data imx95_devtype_data = { > + .identifier = "imx95", > + .attrs = imx95_ddr_perf_events_attrs, > +}; > + > static const struct of_device_id imx_ddr_pmu_dt_ids[] = { > { .compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data }, > + { .compatible = "fsl,imx95-ddr-pmu", .data = &imx95_devtype_data }, > { /* sentinel */ } > }; > MODULE_DEVICE_TABLE(of, imx_ddr_pmu_dt_ids); > @@ -410,6 +438,56 @@ static void imx93_ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1 > writel(pmcfg2, pmu->base + PMCFG2); > } > > +static void imx95_ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1, int cfg2) > +{ > + u32 pmcfg1, pmcfg, offset = 0; > + int event, counter; > + > + event = cfg & 0x000000FF; > + counter = (cfg & 0x0000FF00) >> 8; > + > + pmcfg1 = readl_relaxed(pmu->base + PMCFG1); > + > + if (counter == 2 && event == 73) { > + pmcfg1 |= MX95_PMCFG1_WR_BEAT_FILT_EN; > + offset = PMCFG3; > + } else if (counter == 2 && event != 73) { > + pmcfg1 &= ~MX95_PMCFG1_WR_BEAT_FILT_EN; > + } > + > + if (counter == 3 && event == 73) { > + pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN; > + offset = PMCFG4; > + } else if (counter == 3 && event != 73) { > + pmcfg1 &= ~MX95_PMCFG1_RD_BEAT_FILT_EN; > + } > + > + if (counter == 4 && event == 73) { > + pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN; > + offset = PMCFG5; > + } else if (counter == 4 && event != 73) { > + pmcfg1 &= ~MX95_PMCFG1_RD_BEAT_FILT_EN; > + } > + > + if (counter == 5 && event == 73) { > + pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN; > + offset = PMCFG6; > + } else if (counter == 5 && event != 73) { > + pmcfg1 &= ~MX95_PMCFG1_RD_BEAT_FILT_EN; > + } > + > + writel(pmcfg1, pmu->base + PMCFG1); > + > + if (offset) { > + pmcfg = readl_relaxed(pmu->base + offset); > + pmcfg &= ~(FIELD_PREP(MX95_PMCFG_ID_MASK, 0x3FF) | > + FIELD_PREP(MX95_PMCFG_ID, 0x3FF)); > + pmcfg |= (FIELD_PREP(MX95_PMCFG_ID_MASK, cfg2) | > + FIELD_PREP(MX95_PMCFG_ID, cfg1)); > + writel(pmcfg, pmu->base + offset); > + } > +} > + > static void ddr_perf_event_update(struct perf_event *event) > { > struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); > @@ -490,8 +568,12 @@ static int ddr_perf_event_add(struct perf_event *event, int flags) > hwc->idx = counter; > hwc->state |= PERF_HES_STOPPED; > > - /* read trans, write trans, read beat */ > - imx93_ddr_perf_monitor_config(pmu, cfg, cfg1, cfg2); > + if (is_imx93(pmu)) > + /* read trans, write trans, read beat */ > + imx93_ddr_perf_monitor_config(pmu, cfg, cfg1, cfg2); > + else > + /* write beat, read beat2, read beat1, read beat */ > + imx95_ddr_perf_monitor_config(pmu, cfg, cfg1, cfg2); > > if (flags & PERF_EF_START) > ddr_perf_event_start(event, flags); > -- > 2.34.1 >