Some IPQ6000 SoCs don't have pmic chips, and fused 1.2GHz. Add a separate CPU OPP tables for these SoCs. Signed-off-by: Chukun Pan <amadeus@xxxxxxxxxx> --- arch/arm64/boot/dts/qcom/ipq6000-opp.dtsi | 49 +++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq6000-opp.dtsi diff --git a/arch/arm64/boot/dts/qcom/ipq6000-opp.dtsi b/arch/arm64/boot/dts/qcom/ipq6000-opp.dtsi new file mode 100644 index 000000000000..acb4774da33e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq6000-opp.dtsi @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * IPQ6000 without PMIC (MP5496) CPU OPP tables + */ + +/ { + cpu_opp_table: opp-table-cpu { + compatible = "operating-points-v2-kryo-cpu"; + nvmem-cells = <&cpu_speed_bin>; + opp-shared; + + opp-864000000 { + opp-hz = /bits/ 64 <864000000>; + opp-microvolt = <725000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + }; + + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <787500>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <850000>; + opp-supported-hw = <0x4>; + clock-latency-ns = <200000>; + }; + }; +}; + +&CPU0 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&CPU1 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&CPU2 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&CPU3 { + operating-points-v2 = <&cpu_opp_table>; +}; -- 2.25.1