The div clock register is not modified during jz4740_i2s_hw_params.
Hence, default sampling rates are actually used regardless of
sampling rates input from userspace.
This patch adds support to calculate the value of the divider from
the parameters passed from userspace and update the relevant div
registers
Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@xxxxxxxxxx>
---
V2 changes: Removed a redundant #define
---
sound/soc/jz4740/jz4740-i2s.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c
index d3d45c6..b7a7e82 100644
--- a/sound/soc/jz4740/jz4740-i2s.c
+++ b/sound/soc/jz4740/jz4740-i2s.c
@@ -83,6 +83,8 @@
#define JZ_AIC_I2S_STATUS_BUSY BIT(2)
#define JZ_AIC_CLK_DIV_MASK 0xf
+#define I2SDIV_DV_SHIFT 8
+#define I2SDIV_DV_MASK (0xf << I2SDIV_DV_SHIFT)
struct jz4740_i2s {
struct resource *mem;
@@ -237,10 +239,14 @@ static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream,
{
struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
unsigned int sample_size;
- uint32_t ctrl;
+ uint32_t ctrl, div_reg;
+ int div;
ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
+ div_reg = jz4740_i2s_read(i2s, JZ_REG_AIC_CLK_DIV);
+ div = clk_get_rate(i2s->clk_i2s) / (64 * params_rate(params));
+
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S8:
sample_size = 0;
@@ -264,7 +270,10 @@ static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream,
ctrl |= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET;
}
+ div_reg &= ~I2SDIV_DV_MASK;
+ div_reg |= (div - 1) << I2SDIV_DV_SHIFT;
jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
+ jz4740_i2s_write(i2s, JZ_REG_AIC_CLK_DIV, div_reg);
return 0;
}
--
1.9.1
--
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