On 30/01/2024 13:53, Dragan Cvetic wrote: > Convert AMD (Xilinx) sd-fec bindings to yaml format, so it can validate > dt-entries as well as any future additions to yaml. > Change in clocks is due to IP is itself configurable and > only the first two clocks are in all combinations. The last > 6 clocks can be present in some of them. It means order is > not really fixed and any combination is possible. > Interrupt may or may not be present. > The documentation for sd-fec bindings is now YAML, so update the > MAINTAINERS file. > Update the link to the new yaml file in xilinx_sdfec.rst. > > Signed-off-by: Dragan Cvetic <dragan.cvetic@xxxxxxx> > --- > Changes in v2: > --- > Drop clocks description. > Use "contains:" with enum for optional clock-names and update > comment explaining diference from the original DT binding file. > Remove trailing full stops. > Add more details in sdfec-code description. > Set sdfec-code to "string" not "string-array" > --- > Changes in v3: > Fix a mistake in example, set interrupt type to 0. Why? That's not a correct interrupt type in most of the cases. Was this patch tested? ... > diff --git a/Documentation/devicetree/bindings/misc/xlnx,sd-fec.yaml b/Documentation/devicetree/bindings/misc/xlnx,sd-fec.yaml > new file mode 100644 > index 000000000000..ed87c48a9ee9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/misc/xlnx,sd-fec.yaml > @@ -0,0 +1,136 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/misc/xlnx,sd-fec.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Xilinx SDFEC(16nm) IP > + > +maintainers: > + - Cvetic, Dragan <dragan.cvetic@xxxxxxx> > + - Erim, Salih <salih.erim@xxxxxxx> > + > +description: | Do not need '|' unless you need to preserve formatting. > + The Soft Decision Forward Error Correction (SDFEC) Engine is a Hard IP block > + which provides high-throughput LDPC and Turbo Code implementations. > + The LDPC decode & encode functionality is capable of covering a range of > + customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality > + principally covers codes used by LTE. The FEC Engine offers significant > + power and area savings versus implementations done in the FPGA fabric. > + > + xlnx,sdfec-dout-words: > + description: | > + A value 0 indicates that the DOUT_WORDS interface is > + driven with a fixed value and is not present on the device, a value of 1 > + configures the DOUT_WORDS to be block based, while a value of 2 configures the > + DOUT_WORDS input to be supplied for each AXI transaction. > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1, 2 ] > + > + Just one blank line. Best regards, Krzysztof
