On 24-01-23 19:17:10, Konrad Dybcio wrote:
>
>
> On 1/23/24 12:01, Abel Vesa wrote:
> > Add nodes for all USB controllers and their PHYs for X1E80100 platform.
> >
> > Co-developed-by: Sibi Sankar <quic_sibis@xxxxxxxxxxx>
> > Signed-off-by: Sibi Sankar <quic_sibis@xxxxxxxxxxx>
> > Co-developed-by: Rajendra Nayak <quic_rjendra@xxxxxxxxxxx>
> > Signed-off-by: Rajendra Nayak <quic_rjendra@xxxxxxxxxxx>
> > Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
> > ---
> > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 435 ++++++++++++++++++++++++++++++++-
> > 1 file changed, 432 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > index 2b6c55a486b2..593ead89706c 100644
> > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > @@ -5,11 +5,13 @@
> > #include <dt-bindings/clock/qcom,rpmh.h>
> > #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
> > +#include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
> > #include <dt-bindings/dma/qcom-gpi.h>
> > #include <dt-bindings/interconnect/qcom,icc.h>
> > #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
> > #include <dt-bindings/interrupt-controller/arm-gic.h>
> > #include <dt-bindings/mailbox/qcom-ipcc.h>
> > +#include <dt-bindings/phy/phy-qcom-qmp.h>
> > #include <dt-bindings/power/qcom,rpmhpd.h>
> > #include <dt-bindings/power/qcom-rpmpd.h>
> > #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> > @@ -734,9 +736,9 @@ gcc: clock-controller@100000 {
> > <0>,
> > <0>,
> > <0>,
> > - <0>,
> > - <0>,
> > - <0>;
> > + <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
> > + <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
> > + <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
> > power-domains = <&rpmhpd RPMHPD_CX>;
> > #clock-cells = <1>;
> > @@ -2492,6 +2494,126 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
> > };
> > };
> > + usb_1_ss0_hsphy: phy@fd3000 {
> > + compatible = "qcom,x1e80100-snps-eusb2-phy",
> > + "qcom,sm8550-snps-eusb2-phy";
> > + reg = <0 0x00fd3000 0 0x154>;
> > + #phy-cells = <0>;
> > +
> > + clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
> > + clock-names = "ref";
>
> You use this exact same clock for all HS PHYs. Are you sure?
The USB2 HS PHY should use TCSR_USB2_2_CLKREF_EN, while all of the USB1
SS[1-3] HS PHYs seems they share the TCSR_USB2_1_CLKREF_EN.
>
> > +
> > + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
> > +
> > + status = "disabled";
> > + };
> > +
> > + usb_1_ss0_qmpphy: phy@fd5000 {
> > + compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
> > + reg = <0 0x00fd5000 0 0x4000>;
> > +
> > + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
> > + <&rpmhcc RPMH_CXO_CLK>,
> > + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
> > + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> > + clock-names = "aux",
> > + "ref",
> > + "com_aux",
> > + "usb3_pipe";
> > +
> > + power-domains = <&gcc GCC_USB_0_PHY_GDSC>;
>
> This is likely RPMHPD_MX(A/C)
Nope, this platform has dedicated GDSCs for each of the USB1 SS[1-3] QMP
PHYs.
>
> [...]
>
> > + usb_1_ss2_dwc3: usb@a000000 {
> > + compatible = "snps,dwc3";
> > + reg = <0 0x0a000000 0 0xcd00>;
> > + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
> > + iommus = <&apps_smmu 0x14a0 0x0>;
> > + snps,dis_u2_susphy_quirk;
> > + snps,dis_enblslpm_quirk;
> > + snps,usb3_lpm_capable;
> > + phys = <&usb_1_ss2_hsphy>,
> > + <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>;
> > + phy-names = "usb2-phy",
> > + "usb3-phy";
>
> Should this be marked dma-coherent?
Will add.
>
> Konrad
