On Fri, 15 Dec 2023 06:00:33 +0100, Dragan Simic wrote:
> Add missing cache information to the Rockchip RK3399 SoC dtsi. The specified
> values were derived by hand from the cache size specifications available from
> the RK3399 datasheet; for future reference, here's a brief summary:
>
> - Each Cortex-A72 core has 48 KB of L1 instruction cache and
> 32 KB of L1 data cache available, four-way set associative
> - Each Cortex-A53 core core has 32 KB of instruction cache and
> 32 KB of L1 data cache available, four-way set associative
> - The big (A72) cluster has 1 MB of unified L2 cache available
> - The little (A53) cluster has 512 KB of unified L2 cache available
>
> [...]
Applied, thanks!
[1/1] arm64: dts: rockchip: Add cache information to the SoC dtsi for RK3399
commit: b72633ba5cfa932405832de25d0f0a11716903b4
Best regards,
--
Heiko Stuebner <heiko@xxxxxxxxx>
