Hi Geert,
Thanks for your work.
On 2024-01-25 16:34:41 +0100, Geert Uytterhoeven wrote:
> From: Hai Pham <hai.pham.ud@xxxxxxxxxxx>
>
> Add initial support for the Renesas R-Car V4M (R8A779H0) SoC.
>
> Signed-off-by: Hai Pham <hai.pham.ud@xxxxxxxxxxx>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@xxxxxxxxxxxx>
> ---
> v2:
> - Add vendor-prefixes to DT binding definition header files.
>
> Changes compared to the BSP:
> - Add "-clk" suffix to clock node names,
> - Rename "pmu_a76" node to "pmu-a76",
> - Drop bogus CPU masks from GICv3 PPI interrupt specifiers,
> - Drop hscif0 dmas and dma-names placeholder,
> - Add missing hypervisor virtual timer IRQ to timer node.
> ---
> arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 121 ++++++++++++++++++++++
> 1 file changed, 121 insertions(+)
> create mode 100644 arch/arm64/boot/dts/renesas/r8a779h0.dtsi
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
> new file mode 100644
> index 0000000000000000..a082e2d06b696019
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
> @@ -0,0 +1,121 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the R-Car V4M (R8A779H0) SoC
> + *
> + * Copyright (C) 2023 Renesas Electronics Corp.
> + */
> +
> +#include <dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/power/renesas,r8a779h0-sysc.h>
> +
> +/ {
> + compatible = "renesas,r8a779h0";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + a76_0: cpu@0 {
> + compatible = "arm,cortex-a76";
> + reg = <0>;
> + device_type = "cpu";
> + power-domains = <&sysc R8A779H0_PD_A1E0D0C0>;
> + };
> + };
> +
> + extal_clk: extal-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
> +
> + extalr_clk: extalr-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
> +
> + pmu-a76 {
> + compatible = "arm,cortex-a76-pmu";
> + interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + /* External SCIF clock - to be overridden by boards that provide it */
> + scif_clk: scif-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <0>;
> + };
> +
> + soc: soc {
> + compatible = "simple-bus";
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + cpg: clock-controller@e6150000 {
> + compatible = "renesas,r8a779h0-cpg-mssr";
> + reg = <0 0xe6150000 0 0x4000>;
> + clocks = <&extal_clk>, <&extalr_clk>;
> + clock-names = "extal", "extalr";
> + #clock-cells = <2>;
> + #power-domain-cells = <0>;
> + #reset-cells = <1>;
> + };
> +
> + rst: reset-controller@e6160000 {
> + compatible = "renesas,r8a779h0-rst";
> + reg = <0 0xe6160000 0 0x4000>;
> + };
> +
> + sysc: system-controller@e6180000 {
> + compatible = "renesas,r8a779h0-sysc";
> + reg = <0 0xe6180000 0 0x4000>;
> + #power-domain-cells = <1>;
> + };
> +
> + hscif0: serial@e6540000 {
> + compatible = "renesas,hscif-r8a779h0",
> + "renesas,rcar-gen4-hscif", "renesas,hscif";
> + reg = <0 0xe6540000 0 0x60>;
> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 514>,
> + <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>,
> + <&scif_clk>;
> + clock-names = "fck", "brg_int", "scif_clk";
> + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
> + resets = <&cpg 514>;
> + status = "disabled";
> + };
> +
> + gic: interrupt-controller@f1000000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + #address-cells = <0>;
> + interrupt-controller;
> + reg = <0x0 0xf1000000 0 0x20000>,
> + <0x0 0xf1060000 0 0x110000>;
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + prr: chipid@fff00044 {
> + compatible = "renesas,prr";
> + reg = <0 0xfff00044 0 4>;
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
> + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
> + };
> +};
> --
> 2.34.1
>
>
--
Kind Regards,
Niklas Söderlund
