On Thu, Jan 25, 2024 at 02:50:03PM +0000, Tudor Ambarus wrote: > This will allow devices that require 32 bits register accesses to write > data in chunks of 8 or 16 bits. > > One SoC that requires 32 bit register accesses is the google gs101. A > typical use case is SPI, where the clients can request transfers in words > of 8 bits. Might be good to CC this one to linux-arch if reposting.
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