On Thu, Jan 25, 2024 at 10:55:33AM +0800, Wenhua Lin wrote: > Add sprd,mod attribute, which set the number of different > duty cycles that PWM's waveform could output, to dts. > > Signed-off-by: Wenhua Lin <Wenhua.Lin@xxxxxxxxxx> > --- > Documentation/devicetree/bindings/pwm/pwm-sprd.yaml | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pwm/pwm-sprd.yaml b/Documentation/devicetree/bindings/pwm/pwm-sprd.yaml > index 02e039fee3b4..7c956b840fa1 100644 > --- a/Documentation/devicetree/bindings/pwm/pwm-sprd.yaml > +++ b/Documentation/devicetree/bindings/pwm/pwm-sprd.yaml > @@ -55,6 +55,16 @@ properties: > minItems: 4 > maxItems: 4 > > + sprd,mod: > + $ref: /schemas/types.yaml#/definitions/uint32-array > + minItems: 4 > + maxItems: 4 > + items: > + minimum: 0xFF > + maximum: 0xFFF > + description: | > + The number of different duty cycles that could be set for PWM's waveform output. Why is this not a fixed value for a given SoC? Given the description, it certainly sounds like something that does not vary on a per device basis. Thanks, Conor. > + > "#pwm-cells": > const: 2 > > @@ -63,6 +73,7 @@ required: > - reg > - clocks > - clock-names > + - sprd,mod > > additionalProperties: false > > @@ -88,6 +99,7 @@ examples: > <&ext_26m>, > <&ext_26m>, > <&ext_26m>; > + sprd,mod = <0xFF 0x1FF 0x3FF 0xFFF>; > #pwm-cells = <2>; > }; > > -- > 2.17.1 >
Attachment:
signature.asc
Description: PGP signature
