Am 25.01.24 um 07:05 schrieb Wadim Egorov:
Am 24.01.24 um 18:28 schrieb Stefan Wahren:
Hello Mathieu,
Am 24.01.24 um 14:48 schrieb Mathieu Othacehe:
Hello Stefan,
Defining line names should be fine. But I would still prefer to have
the muxing in an overlay bound to a specific use case.
I'm fine with this. Unfortunately Mathieu dropped the line names in V5
today :-(
AFAIR reviewers should have 2 weeks time maximum. This was just 2
days.
I am sorry but it is not easy for me to deal with contradictory
input. I
chose to remove the gpio-line-names even though it also seemed like a
nice addition to me. The idea was to not interfere with Phytec plans in
the future.
tbh sending v5 before the discussion between Wadim and me was finished
made it more complicated. Please keep in mind that some reviewers do
this in their spare time, so a response could take some time.
In this particular case Wadim and me agreed on a solution, so no action
from your side was necessary except a little bit patience.
The reason why i suggested the gpio-line-names in the first place is
that users doesn't need to care about different versions of the DT files
(except the downstream one). Changing the line names afterwards leads to
confusion.
So before we discuss on a v6, just a question: are on the X16 connector
just 2 pins muxable as GPIO? This is hard to believe.
In theory you can use more of the Pins as GPIOs. But at this point I
should mention that the Segin board became slightly more complicated
since it started to support more SoMs with different SoCs. We have
routings for various pins to help with the compatibility. So the
naming in the schematics is not really trivial. And IMO the dt should
follow the naming of the schematics.
Thanks for the explanation
I would prefer to go with v5 without having any namings for now.
Okay
Regards,
Wadim
