Hello, This series fixes a longstanding but recently identified issue on Qcom platforms regarding the use of PCIE_AUX_CLK in PCIe PHY nodes. While trying to remove the PCIE_GDSC power domain from the PCIe PHY nodes, Johan reported [1] that he encountered "gcc_pcie_3b_aux_clk status stuck at 'off'" issue on the X13s while powering up the PCIe PHY without enabling the PCIE_GDSC. This confirmed that the "gcc_pcie_3b_aux_clk" depends on PCIE_GDSC. But the name of the clock implies that it is used by the PCIe controller. So I checked with Qcom internally and confirmed that this clock belongs to the controller, not PHY. But on some SoCs, there is a separate PCIE_PHY_AUX_CLK for the PHY to keep the link stable during the PCIe L1SS state. But due to some reasons, that clock is powered by PCIE_GDSC. So to conclude, PCIE_AUX_CLK belongs to the controller and it depends on PCIE_GDSC, so it should be removed from the PHY nodes. On the other hand, PCIE_PHY_AUX_CLK belongs to the PHY and it also depends on the PCIE_GDSC. So for the PHY instances that require this clock, PCIE_GDSC should be added as a second power domain along with MX domain which is applicable to all PHYs. This series removes the PCIE_AUX_CLK from PCIe PHY nodes of all SoCs and also makes the changes to the bindings to reflect the same. I will also submit a followup series to fix the PHY power domain across all SoCs. NOTE: I haven't added the Fixes tag on purpose, since the patches are getting backported by the stable team whenever the tag is present and if both the binding and dts patches didn't get backported to a release, then it will cause ABI break. - Mani [1] https://lore.kernel.org/lkml/ZY6sh8nlEUyEfL0u@xxxxxxxxxxxxxxxxxxxx/ Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> --- Manivannan Sadhasivam (14): dt-bindings: phy: qcom,ipq8074-qmp-pcie: Drop PCIE_AUX_CLK from pcie_phy node arm64: dts: qcom: ipq6018: Drop PCIE_AUX_CLK from pcie_phy node arm64: dts: qcom: ipq8074: Drop PCIE_AUX_CLK from pcie_phy nodes dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Fix the usage of aux clk dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document missing compatible for SM8350 3x2 PHY phy: qcom: qmp-pcie: Add a new compatible for SC7280 SoC phy: qcom: qmp-pcie: Add a comment to clarify the use of "aux and "phy_aux" clocks arm64: dts: qcom: sc7280: Drop PCIE_AUX_CLK from pcie_phy node arm64: dts: qcom: sc8280xp: Drop PCIE_AUX_CLK from pcie_phy nodes arm64: dts: qcom: sm8350: Drop PCIE_AUX_CLK from pcie_phy nodes arm64: dts: qcom: sm8450: Drop PCIE_AUX_CLK from pcie_phy node arm64: dts: qcom: sm8550: Drop PCIE_AUX_CLK from pcie_phy node arm64: dts: qcom: sm8650: Drop PCIE_AUX_CLK from pcie_phy node arm64: dts: qcom: sa8775p: Drop PCIE_AUX_CLK from pcie_phy nodes .../bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml | 9 +-- .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 81 ++++++++++++++-------- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 6 +- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ++-- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 14 ++-- arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 +-- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 25 +++---- arch/arm64/boot/dts/qcom/sm8350.dtsi | 10 ++- arch/arm64/boot/dts/qcom/sm8450.dtsi | 6 +- arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 +- arch/arm64/boot/dts/qcom/sm8650.dtsi | 6 +- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 13 +++- 12 files changed, 104 insertions(+), 92 deletions(-) --- base-commit: 6613476e225e090cc9aad49be7fa504e290dd33d change-id: 20240122-pcie-aux-clk-fix-094bc77a16ba Best regards, -- Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
