From: "zhifeng.tang" <zhifeng.tang@xxxxxxxxxx>
In most of Sprd SOCs,The clock controller register block also
contains reset bits for some of these peripherals,so reset
controller and clock provider are combined together as a block,
and put it under the driver/clk/.
Signed-off-by: zhifeng.tang <zhifeng.tang@xxxxxxxxxx>
---
arch/arm64/boot/dts/sprd/ums512.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/sprd/ums512.dtsi b/arch/arm64/boot/dts/sprd/ums512.dtsi
index 024be594c47d..08d0adf6624c 100644
--- a/arch/arm64/boot/dts/sprd/ums512.dtsi
+++ b/arch/arm64/boot/dts/sprd/ums512.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/clock/sprd,ums512-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/sprd,ums512-reset.h>
/ {
interrupt-parent = <&gic>;
@@ -182,6 +183,7 @@
clocks = <&ext_26m>;
clock-names = "ext-26m";
#clock-cells = <1>;
+ #reset-cells = <1>;
};
};
@@ -316,6 +318,7 @@
clocks = <&ext_26m>;
clock-names = "ext-26m";
#clock-cells = <1>;
+ #reset-cells = <1>;
};
};
@@ -333,6 +336,7 @@
clocks = <&ext_26m>;
clock-names = "ext-26m";
#clock-cells = <1>;
+ #reset-cells = <1>;
};
};
@@ -348,6 +352,7 @@
compatible = "sprd,ums512-audcpapb-gate";
reg = <0x0 0x300>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
};
@@ -363,6 +368,7 @@
compatible = "sprd,ums512-audcpahb-gate";
reg = <0x0 0x300>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
};
@@ -380,6 +386,7 @@
clock-names = "ext-26m";
reg = <0x0 0x100>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
};
@@ -401,6 +408,7 @@
compatible = "sprd,ums512-mm-gate-clk";
reg = <0x0 0x3000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
};
@@ -416,6 +424,7 @@
compatible = "sprd,ums512-apapb-gate";
reg = <0x0 0x3000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
};
--
2.17.1
