Hi On 1/22/24 10:57, Rafał Miłecki wrote:
This is already added in this commit https://github.com/torvalds/linux/commit/cb57fae479be41d1233f5a49d4760de9a5692b6e. But brcmnand nand controller has dedicated pin for WP and don't use GPIO. So it does not apply to here. Basically brcmnand controller handle the WP inside the controller and its driver.On 2024-01-18 20:53, dregan@xxxxxxxxxxxx wrote:@@ -111,6 +113,17 @@ properties: earlier versions of this core that include WP type: boolean + brcm,nand-use-wp: + description: + Use this property to indicate if board design uses + controller's write protection feature and connects its + NAND_WPb pin to nand chip's WP_L pin. Driver defaults to + use this feature when this property does not exist. + Set to 0 if WP pins are not connected and feature is not + used. Set to 1 if WP pins are connected and feature is used. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + patternProperties: "^nand@[a-f0-9]$": type: objectPlease take a look at: [PATCH 1/2] dt-bindings: mtd: brcmnand: add "no-wp" property https://lore.kernel.org/linux-mtd/20211109115215.5bcef0db@xps13/T/ Miquel suggested a generic property applicable to all raw NANDs for such purpose. Unfortunately I dropped the ball on that.
brcm,nand-has-wp is SoC level flag and it actually is only needed for some rare earlier versions of the controller. I don't want to break that so I added this board level flag brcm,nand-use-wp for per board control of the WP pin usage. As you know many BCMBCA reference boards (like the 4908 based) do not connect WP pin so customer follow the same. You can use this flag in the Asus GT-AC5300 board dts as you intended to address in your patch.
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