On 15:14-20240118, Chintan Vankar wrote:
> From: Siddharth Vadapalli <s-vadapalli@xxxxxx>
>
> J784S4 SoC has a 9 port Ethernet Switch instance with 8 external
> ports and 1 host port, referred to as CPSW9G.
>
> Add device-tree nodes for CPSW9G and disable it by default.
> Device-tree overlays will be used to enable it.
>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@xxxxxx>
> Signed-off-by: Chintan Vankar <c-vankar@xxxxxx>
> ---
> arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 114 +++++++++++++++++++++
> 1 file changed, 114 insertions(+)
Any reason why we cant squash this to previous patch with
something like "Add main cpsw nodes" ?
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> index 191fdbe02877..9aebce8a51ab 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> @@ -54,6 +54,13 @@ cpsw1_phy_gmii_sel: phy@4034 {
> #phy-cells = <1>;
> };
>
> + cpsw0_phy_gmii_sel: phy@4044 {
> + compatible = "ti,j784s4-cpsw9g-phy-gmii-sel";
> + ti,qsgmii-main-ports = <7>, <7>;
> + reg = <0x4044 0x20>;
> + #phy-cells = <1>;
> + };
> +
> serdes_ln_ctrl: mux-controller@4080 {
> compatible = "reg-mux";
> reg = <0x00004080 0x30>;
> @@ -1248,6 +1255,113 @@ cpts@310d0000 {
> };
> };
>
> + main_cpsw0: ethernet@c000000 {
> + compatible = "ti,j784s4-cpswxg-nuss";
> + reg = <0x00 0xc000000 0x00 0x200000>;
> + reg-names = "cpsw_nuss";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>;
> + dma-coherent;
> + clocks = <&k3_clks 64 0>;
> + clock-names = "fck";
> + power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
> +
> + dmas = <&main_udmap 0xca00>,
> + <&main_udmap 0xca01>,
> + <&main_udmap 0xca02>,
> + <&main_udmap 0xca03>,
> + <&main_udmap 0xca04>,
> + <&main_udmap 0xca05>,
> + <&main_udmap 0xca06>,
> + <&main_udmap 0xca07>,
> + <&main_udmap 0x4a00>;
> + dma-names = "tx0", "tx1", "tx2", "tx3",
> + "tx4", "tx5", "tx6", "tx7",
> + "rx";
> +
> + status = "disabled";
> +
> + ethernet-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + main_cpsw0_port1: port@1 {
> + reg = <1>;
> + label = "port1";
> + ti,mac-only;
> + status = "disabled";
> + };
> +
> + main_cpsw0_port2: port@2 {
> + reg = <2>;
> + label = "port2";
> + ti,mac-only;
> + status = "disabled";
> + };
> +
> + main_cpsw0_port3: port@3 {
> + reg = <3>;
> + label = "port3";
> + ti,mac-only;
> + status = "disabled";
> + };
> +
> + main_cpsw0_port4: port@4 {
> + reg = <4>;
> + label = "port4";
> + ti,mac-only;
> + status = "disabled";
> + };
> +
> + main_cpsw0_port5: port@5 {
> + reg = <5>;
> + label = "port5";
> + status = "disabled";
> + };
> +
> + main_cpsw0_port6: port@6 {
> + reg = <6>;
> + label = "port6";
> + status = "disabled";
> + };
> +
> + main_cpsw0_port7: port@7 {
> + reg = <7>;
> + label = "port7";
> + status = "disabled";
> + };
> +
> + main_cpsw0_port8: port@8 {
> + reg = <8>;
> + label = "port8";
> + status = "disabled";
> + };
> + };
> +
> + main_cpsw0_mdio: mdio@f00 {
> + compatible = "ti,cpsw-mdio","ti,davinci_mdio";
> + reg = <0x00 0xf00 0x00 0x100>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&k3_clks 64 0>;
> + clock-names = "fck";
> + bus_freq = <1000000>;
> + status = "disabled";
> + };
> +
> + cpts@3d000 {
> + compatible = "ti,am65-cpts";
> + reg = <0x00 0x3d000 0x00 0x400>;
> + clocks = <&k3_clks 64 3>;
> + clock-names = "cpts";
> + interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "cpts";
> + ti,cpts-ext-ts-inputs = <4>;
> + ti,cpts-periodic-outputs = <2>;
> + };
> + };
> +
> main_cpsw1: ethernet@c200000 {
> compatible = "ti,j721e-cpsw-nuss";
> #address-cells = <2>;
> --
> 2.34.1
>
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
