On 1/16/24 16:20, Krzysztof Kozlowski wrote:
On 16/01/2024 12:11, Dragan Cvetic wrote:
Convert AMD (Xilinx) sd-fec bindings to yaml format, so it can validate
dt-entries as well as any future additions to yaml.
Conversion txt to yamal is done "one to one", no new changes in txt file
has been made.
Reviewed-by: Michal Simek <michal.simek@xxxxxxx>
Where? Please provide a link. Judging by amount of issues here, I have
some doubts, because I know Michal writes good schema. :)
I reviewed it internally. But yes, I didn't provide this line.
And never said that 2/2 should be separate patch too. :-)
Signed-off-by: Dragan Cvetic <dragan.cvetic@xxxxxxx>
All your patches were marked as spam. Please work with your IT to
resolve it, otherwise your future submissions might get ignored by me,
because I will just not see them.
---
.../devicetree/bindings/misc/xlnx,sd-fec.txt | 58 --------
.../devicetree/bindings/misc/xlnx,sd-fec.yaml | 132 ++++++++++++++++++
2 files changed, 132 insertions(+), 58 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/misc/xlnx,sd-fec.txt
create mode 100644 Documentation/devicetree/bindings/misc/xlnx,sd-fec.yaml
Please use scripts/get_maintainers.pl to get a list of necessary people
and lists to CC (and consider --no-git-fallback argument). It might
happen, that command when run on an older kernel, gives you outdated
entries. Therefore please be sure you base your patches on recent Linux
kernel.
Looks like you either based it on some downstream tree (don't do this)
or used random list of recipients (also don't do this).
Please reach to other AMD folks to explain you how patches should be
submitted. There are a lot of experienced guys there, so use them.
diff --git a/Documentation/devicetree/bindings/misc/xlnx,sd-fec.txt b/Documentation/devicetree/bindings/misc/xlnx,sd-fec.txt
deleted file mode 100644
index e3289634fa30..000000000000
--- a/Documentation/devicetree/bindings/misc/xlnx,sd-fec.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-* Xilinx SDFEC(16nm) IP *
-
...
- };
diff --git a/Documentation/devicetree/bindings/misc/xlnx,sd-fec.yaml b/Documentation/devicetree/bindings/misc/xlnx,sd-fec.yaml
new file mode 100644
index 000000000000..05bc01cb5075
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/xlnx,sd-fec.yaml
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/xlnx,sd-fec.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx SDFEC(16nm) IP
+
+maintainers:
+ - Cvetic, Dragan <dragan.cvetic@xxxxxxx>
+ - Erim, Salih <salih.erim@xxxxxxx>
+
+description: |
+ The Soft Decision Forward Error Correction (SDFEC) Engine is a Hard IP block
+ which provides high-throughput LDPC and Turbo Code implementations.
+ The LDPC decode & encode functionality is capable of covering a range of
+ customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality
+ principally covers codes used by LTE. The FEC Engine offers significant
+ power and area savings versus implementations done in the FPGA fabric.
+
+properties:
+ compatible:
+ const: xlnx,sd-fec-1.1
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ description: List of clock specifiers.
Drop description, it's obvious. Do you see it anywhere in existing code?
+ additionalItems: true
Drop, you cannot have it.
+ minItems: 2
+ maxItems: 8
Drop maxItems, not needed.
+ items:
+ - description: Main processing clock for processing core.
Drop trailing full-stops.
+ - description: AXI4-Lite memory-mapped slave interface clock.
+ - description: Control input AXI4-Stream Slave interface clock.
+ - description: DIN AXI4-Stream Slave interface clock.
+ - description: Status output AXI4-Stream Master interface clock.
+ - description: DOUT AXI4-Stream Master interface clock.
+ - description: DIN_WORDS AXI4-Stream Slave interface clock
+ - description: DOUT_WORDS AXI4-Stream Master interface clock
+
+ clock-names:
+ additionalItems: true
Nope
+ minItems: 2
+ maxItems: 8
Nope
+ items:
+ - const: core_clk
+ - const: s_axi_aclk
+ - enum:
+ - s_axis_ctrl_aclk
+ - s_axis_din_aclk
+ - m_axis_status_aclk
+ - m_axis_dout_aclk
+ - s_axis_din_words_aclk
+ - m_axis_dout_words_aclk
Why order is not enforced?
Let me comment this one. Based on my discussion with Dragan IP itself is
configurable and only the first two clocks are in all combinations. But based on
his description that last 6 clocks can be present in some of them.
It means order is not really fixed and any combination is possible.
That's why I have suggested him to use this description because I didn't find
any better one.
I actually tested this schema here but didn't get a feedback on it yet.
https://lore.kernel.org/r/3e86244a840a45c970289ba6d2fa700a74f5b259.1705051222.git.michal.simek@xxxxxxx
It means not sure about not defining maxItems but when I don't do it it is not
passing dtbs_check.
Thanks,
Michal
