On Tue, Jan 16, 2024 at 10:34:22AM +0530, Krishna Chaitanya Chundru wrote:
>
>
> On 1/12/2024 9:29 PM, Johan Hovold wrote:
> > On Fri, Jan 12, 2024 at 07:52:02PM +0530, Krishna chaitanya chundru wrote:
> >> CPU-PCIe path consits for registers PCIe BAR space, config space.
> >
> > consits?
> >
> >> As there is less access on this path compared to pcie to mem path
> >> add minimum vote i.e GEN1x1 bandwidth always.
> >
> > gen1 bandwidth can't be right.
> There is no recommended value we need vote for this path, as there is
> BAR and config space in this path we are voting for GEN1x1.
I can see that, but that does not explain why you used those seemingly
arbitrary numbers or why you think that's correct.
> Please suggest a recommended value for this path if the GEN1x1 is high.
No, you submitted the patch and you work for Qualcomm. You need to
figure out what the value should be. All I can say is that the gen1
value is likely not correct and therefore confusing.
> >> In suspend remove the cpu vote after register space access is done.
> >>
> >> Fixes: c4860af88d0c ("PCI: qcom: Add basic interconnect support")
> >> cc: stable@xxxxxxxxxxxxxxx
> >
> > This does not look like a fix so drop the above.
> >
> > The commit you refer to explicitly left this path unconfigured for now
> > and only added support for the configuring the mem path as needed on
> > sc8280xp which otherwise would crash.
> Without this path vote BAR and config space can result NOC timeout
> errors, we are surviving because of other driver vote for this path.
> For that reason we added a fix tag.
Ok, then mention that in the commit message so that it becomes more
clear why this is needed and whether this should be considered a fix. As
it stands, the commit message makes this look like a new feature.
And the above Fixes tag is incorrect either way as that commit did not
introduce any issue.
Johan
