Hi Geert,
Thanks for your work.
On 2024-01-08 16:33:46 +0100, Geert Uytterhoeven wrote:
> R-Car V4H and V4M have a second Frequency Control Register C.
> Add support for this by treating bit field offsets beyond 31 as
> referring to the second register.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@xxxxxxxxxxxx>
> ---
> Tested by enabling CLOCK_ALLOW_WRITE_DEBUGFS and checking the impact of
> CPU core clk rate on CPU core speed on R-Car V4M.
> ---
> drivers/clk/renesas/rcar-gen4-cpg.c | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/renesas/rcar-gen4-cpg.c b/drivers/clk/renesas/rcar-gen4-cpg.c
> index c68d8b987054131b..a2bbdad021ed8e95 100644
> --- a/drivers/clk/renesas/rcar-gen4-cpg.c
> +++ b/drivers/clk/renesas/rcar-gen4-cpg.c
> @@ -179,7 +179,8 @@ static struct clk * __init cpg_pll_clk_register(const char *name,
> */
> #define CPG_FRQCRB 0x00000804
> #define CPG_FRQCRB_KICK BIT(31)
> -#define CPG_FRQCRC 0x00000808
> +#define CPG_FRQCRC0 0x00000808
> +#define CPG_FRQCRC1 0x000008e0
>
> struct cpg_z_clk {
> struct clk_hw hw;
> @@ -304,7 +305,12 @@ static struct clk * __init cpg_z_clk_register(const char *name,
> init.parent_names = &parent_name;
> init.num_parents = 1;
>
> - zclk->reg = reg + CPG_FRQCRC;
> + if (offset < 32) {
> + zclk->reg = reg + CPG_FRQCRC0;
> + } else {
> + zclk->reg = reg + CPG_FRQCRC1;
> + offset -= 32;
> + }
> zclk->kick_reg = reg + CPG_FRQCRB;
> zclk->hw.init = &init;
> zclk->mask = GENMASK(offset + 4, offset);
> --
> 2.34.1
>
>
--
Kind Regards,
Niklas Söderlund
