On Wed, 2023-11-29 at 14:22 +0100, AngeloGioacchino Del Regno wrote:
> Il 14/09/23 14:10, Mark Tseng ha scritto:
> > The original CCI OPP table's lowest frequency 500 MHz is too low
> > and causes
> > system stalls. Increase the frequency range to 1.05 GHz ~ 1.4 GHz
> > and adjust
> > the OPPs accordingly.
> >
> > Fixes: 32dfbc03fc26 ("arm64: dts: mediatek: mt8186: Add CCI node
> > and CCI OPP table")
> >
> > Signed-off-by: Mark Tseng <chun-jen.tseng@xxxxxxxxxxxx>
>
> You ignored my comment [1] on the v1 of this patch.
>
> Besides, I think that you should at least keep the 500MHz frequency
> for a
> sleep-only/idle OPP to save power.
>
> It would also be helpful to understand why you chose this new
> frequency range,
> so if you can, please put some numbers in the commit description,
> showing the
> stall in terms of requested BW vs actual BW (as I'd imagine that a 2x
> increase
> in CCI frequency means that we need *twice* the bandwidth compared to
> what we
> have for the workloads that are stalling the system).
>
Hi AngeloGioacchino Del Regno,
Thanks your reminder this issue. After ajdustment CCI OPP, we also do
power test benchmark and the result is PASS.
The original CCI table has stall issue. When the Big CPU frequency set
on 2.05G and CCI frequency keep on 500MHz then run CTS MediaTest will
system stall then trigger watchdog reset SoC.
The CPU and CCI frequency setting are not in the same driver. So it
will have timing issue cause CPU stall side effect.
BRs,
Mark Tseng
> [1]:
> https://lore.kernel.org/all/799325f5-29b5-f0c0-16ea-d47c06830ed3@xxxxxxxxxxxxx/
>
> Regards,
> Angelo
