Hi Christian and Robert,
thank you for this great work!
Let me ask a couple of questions regarding the phy package conception.
Please find them below.
On 26.11.2023 03:53, Christian Marangi wrote:
Document ethernet PHY package nodes used to describe PHY shipped in
bundle of 4-5 PHY. The special node describe a container of PHY that
share common properties. This is a generic schema and PHY package
should create specialized version with the required additional shared
properties.
Example are PHY package that have some regs only in one PHY of the
package and will affect every other PHY in the package, for example
related to PHY interface mode calibration or global PHY mode selection.
The PHY package node MUST declare the base address used by the PHY driver
for global configuration by calculating the offsets of the global PHY
based on the base address of the PHY package and declare the
"ethrnet-phy-package" compatible.
Each reg of the PHY defined in the PHY package node is absolute and will
reference the real address of the PHY on the bus.
Signed-off-by: Christian Marangi <ansuelsmth@xxxxxxxxx>
---
.../bindings/net/ethernet-phy-package.yaml | 75 +++++++++++++++++++
1 file changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/ethernet-phy-package.yaml
diff --git a/Documentation/devicetree/bindings/net/ethernet-phy-package.yaml b/Documentation/devicetree/bindings/net/ethernet-phy-package.yaml
new file mode 100644
index 000000000000..244d4bc29164
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/ethernet-phy-package.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/ethernet-phy-package.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ethernet PHY Package Common Properties
+
+maintainers:
+ - Christian Marangi <ansuelsmth@xxxxxxxxx>
+
+description:
+ This schema describe PHY package as simple container for
+ a bundle of PHYs that share the same properties and
+ contains the PHYs of the package themself.
+
+ Each reg of the PHYs defined in the PHY package node is
+ absolute and describe the real address of the PHY on the bus.
+
+properties:
+ $nodename:
+ pattern: "^ethernet-phy-package(@[a-f0-9]+)?$"
+
+ compatible:
+ const: ethernet-phy-package
+
+ reg:
+ minimum: 0
+ maximum: 31
+ description:
+ The base ID number for the PHY package.
+ Commonly the ID of the first PHY in the PHY package.
+
+ Some PHY in the PHY package might be not defined but
+ still exist on the device (just not attached to anything).
+ The reg defined in the PHY package node might differ and
+ the related PHY might be not defined.
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+patternProperties:
+ ^ethernet-phy(@[a-f0-9]+)?$:
+ $ref: ethernet-phy.yaml#
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: true
+
+examples:
+ - |
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-phy-package@16 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "ethernet-phy-package";
+ reg = <0x16>;
+
+ ethernet-phy@16 {
+ reg = <0x16>;
+ };
+
+ phy4: ethernet-phy@1a {
+ reg = <0x1a>;
+ };
+ };
+ };
So, we ended up on a design where we use the predefined compatible
string 'ethernet-phy-package' to recognize a phy package inside the
of_mdiobus_register() function. During the V1 discussion, Vladimir came
up with the idea of 'ranges' property usage [1]. Can we use 'ranges' to
recognize a phy package in of_mdiobus_register()? IMHO this will give us
a clear DT solution. I mean 'ranges' clearly indicates that child nodes
are in the same address range as the parent node. Also we can list all
child addresses in 'reg' to mark them occupied.
mdio {
...
ethernet-phy-package@16 {
compatible = "qcom,qca8075";
reg = <0x16>, <0x17>, <0x18>, <0x19>, <0x1a>;
ranges;
...
ethernet-phy@16 {
reg = <0x16>;
};
ethernet-phy@1a {
reg = <0x1a>;
};
};
};
Did you find some issues with the 'ranges' conception?
And I would like to ask you about another issue raised by Vladimir [1].
These phy chips become SoC with all these built-in PHYs, PCSs, clocks,
interrupt controllers, etc. Should we address this now? Or should we go
with the proposed solution for now and postpone modeling of other
peripherals until we get a real hardware, as Andrew suggested?
I'm asking because it looks like we have got a real hardware. Luo
currently trying to push QCA8084 (multi-phy/switch chip) support, and
this chip exactly contains a huge clock/reset controller [2,3].
1. https://lore.kernel.org/lkml/20231124165923.p2iozsrnwlogjzua@skbuf //
Re: [net-next RFC PATCH 03/14] dt-bindings: net: document ethernet PHY
package nodes
2.
https://lore.kernel.org/lkml/20231215074005.26976-1-quic_luoj@xxxxxxxxxxx
// [PATCH v8 00/14] add qca8084 ethernet phy driver
3.
https://lore.kernel.org/lkml/20231104034858.9159-1-quic_luoj@xxxxxxxxxxx
// [PATCH v12 0/4] add clock controller of qca8386/qca8084
--
Sergey
