On 1/5/24 7:52 AM, Andrew Lunn wrote:
On Fri, Jan 05, 2024 at 04:48:31AM +0200, Sergey Ryazanov wrote:
Hi Luo,
thank you for explaining the case in such details. I also have checked the
related DTSs in the Linaro repository to be more familiar with the I/O mem
layout. Specifically I checked these two, hope they are relevant to the
discussion:
https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4.r3/arch/arm64/boot/dts/qcom/ipq5332.dtsi
https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4.r3/arch/arm64/boot/dts/qcom/ipq9574.dtsi
Please find my comments below.
Hi Sergey
There is a second thread going on, focused around the quad PHY. See:
https://lore.kernel.org/netdev/60b9081c-76fa-4122-b7ae-5c3dcf7229f9@xxxxxxx/
Since it is very hard to get consistent information out of Luo, he has
annoyed nearly all the PHY maintainers and all the DT maintainers, i'm
going back to baby steps, focusing on just the quad pure PHY, and
trying to get that understood and correctly described in DT.
However, does Linaro have any interest in just taking over this work,
or mentoring Luo?
I will reach out to Qualcomm to discuss options here. We can
certainly offer to mentor, and I think we might even be able to
take over the work. But I won't be able to get any resolution
on this until next week.
Jie Luo, please hold off on further posts on this for a little
while.
I will report back once I've been able to discuss this with
folks at Qualcomm.
-Alex
Andrew
