On Wed, Dec 27, 2023 at 11:28:28PM +0100, Konrad Dybcio wrote:
> The CLKREQ pin should not be muxed to its active function when the RC
> is asleep.
You forgot to explain *why* you think this is needed.
Note that this is only appears to be done for one upstream Qualcomm SoC
(msm8996) currently, and that, notably, there is no driver support for
actually changing the pin state.
> Add the missing pin sleep states to resolve that.
> Fixes: d907fe5acbf1 ("arm64: dts: qcom: sc8280xp-crd: enable WiFi controller")
> Fixes: 17e2ccaf65d1 ("arm64: dts: qcom: sc8280xp-crd: enable SDX55 modem")
> Fixes: 6a1ec5eca73c ("arm64: dts: qcom: sc8280xp-crd: enable NVMe SSD")
So not sure these Fixes tags are warranted either.
> Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 78 ++++++++++++++++++++-----------
> 1 file changed, 51 insertions(+), 27 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> index ffc4406422ae..58c0c2d10cb3 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> @@ -530,8 +530,9 @@ &pcie2a {
>
> vddpe-3v3-supply = <&vreg_nvme>;
>
> - pinctrl-names = "default";
> - pinctrl-0 = <&pcie2a_default>;
> + pinctrl-0 = <&pcie2a_default>, <&pcie2a_clkreq_default>;
> + pinctrl-1 = <&pcie2a_default>, <&pcie2a_clkreq_sleep>;
> + pinctrl-names = "default", "sleep";
Johan
