On Wed, Dec 27, 2023 at 11:28:26PM +0100, Konrad Dybcio wrote:
> The PCIe GDSCs are only related to the RCs. The PCIe PHYs on the other
> hand, are powered by VDD_MX and their specific VDDA_PHY/PLL regulators.
No, that does not seem to be entirely correct. I added the power-domains
here precisely because they were needed to enable the PHYs.
This is something I stumbled over when trying to figure out how to
add support for the second lane pair (i.e. four-lane mode), and I just
went back and confirmed that this is still the case.
If you try to enable one of these PHYs without the corresponding GDSC
being enabled, you end up with:
[ 37.709324] ------------[ cut here ]------------
[ 37.718196] gcc_pcie_3b_aux_clk status stuck at 'off'
[ 37.718205] WARNING: CPU: 4 PID: 482 at drivers/clk/qcom/clk-branch.c:86 clk_branch_wait+0x144/0x15c
Now, you may or may not want to describe the above in the devicetree,
but this makes it sound like you're trying to work around an issue with
the current Linux implementation.
> Fix the power-domains assignment to stop potentially toggling the GDSC
> unnecessarily.
Nothing is being toggled unnecessarily, and generally this is just
another use count increment.
> Fixes: 813e83157001 ("arm64: dts: qcom: sc8280xp/sa8540p: add PCIe2-4 nodes")
So not sure a Fixes tag is warranted either.
> @@ -1895,7 +1895,7 @@ pcie3b_phy: phy@1c0e000 {
> assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
> assigned-clock-rates = <100000000>;
>
> - power-domains = <&gcc PCIE_3B_GDSC>;
> + power-domains = <&rpmhpd SC8280XP_MX>;
>
> resets = <&gcc GCC_PCIE_3B_PHY_BCR>;
> reset-names = "phy";
Johan
