On 26.12.2023 09:08, Qiang Yu wrote: > On sm8550, synopsys MSI controller supports 256 MSI interrupts. Hence, > enable all GIC interrupts required by MSI controller for PCIe0 and PCIe1. > > Signed-off-by: Qiang Yu <quic_qianyu@xxxxxxxxxxx> > --- Thanks for digging this up, could you check the same for other platforms too? Particularly for the compute ones which heavily depend on PCIe.. > arch/arm64/boot/dts/qcom/sm8550.dtsi | 24 ++++++++++++++++++++---- > 1 file changed, 20 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi > index ee1ba5a..80e31fb 100644 > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi > @@ -1713,8 +1713,16 @@ > linux,pci-domain = <0>; > num-lanes = <2>; > > - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; > - interrupt-names = "msi"; > + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "msi0", "msi1", "msi2", "msi3", > + "msi4", "msi5", "msi6", "msi7"; Please make it one per line, like the interrupts entries. Konrad
