Add bindings for the South-West clock and reset generator (SWCRG) on JH8100 SoC. Signed-off-by: Sia Jee Heng <jeeheng.sia@xxxxxxxxxxxxxxxx> Reviewed-by: Ley Foon Tan <leyfoon.tan@xxxxxxxxxxxxxxxx> --- .../bindings/clock/starfive,jh8100-swcrg.yaml | 64 +++++++++++++++++++ .../dt-bindings/clock/starfive,jh8100-crg.h | 12 ++++ .../dt-bindings/reset/starfive,jh8100-crg.h | 8 +++ 3 files changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-swcrg.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jh8100-swcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh8100-swcrg.yaml new file mode 100644 index 000000000000..287dff7e91e3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh8100-swcrg.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh8100-swcrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH8100 South-West Clock And Reset Generator + +maintainers: + - Sia Jee Heng <jeeheng.sia@xxxxxxxxxxxxxxxx> + +properties: + compatible: + const: starfive,jh8100-swcrg + + reg: + maxItems: 1 + + clocks: + items: + - description: APB_BUS clock from SYSCRG + - description: VDEC_ROOT clock from SYSCRG + - description: FLEXNOC1 clock from SYSCRG + + clock-names: + items: + - const: apb_bus + - const: vdec_root + - const: flexnoc1 + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive,jh8100-crg.h> for valid indices. + + '#reset-cells': + const: 1 + description: + See <dt-bindings/reset/starfive,jh8100-crg.h> for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/starfive,jh8100-crg.h> + + clock-controller@12720000 { + compatible = "starfive,jh8100-swcrg"; + reg = <0x12720000 0x10000>; + clocks = <&syscrg JH8100_SYSCLK_APB_BUS>, + <&syscrg JH8100_SYSCLK_VDEC_ROOT>, + <&syscrg JH8100_SYSCLK_FLEXNOC1>; + clock-names = "apb_bus", "vdec_root", "flexnoc1"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jh8100-crg.h b/include/dt-bindings/clock/starfive,jh8100-crg.h index c37b42f3eacd..7b337c1495be 100644 --- a/include/dt-bindings/clock/starfive,jh8100-crg.h +++ b/include/dt-bindings/clock/starfive,jh8100-crg.h @@ -339,4 +339,16 @@ #define JH8100_NECLK_CAN1_ICG_EN 173 #define JH8100_NECLK_SMBUS0_ICG_EN 174 +/* SWCRG clocks */ +#define JH8100_SWCLK_JPEG_AXI 0 +#define JH8100_SWCLK_VC9000DJ_AXI 1 +#define JH8100_SWCLK_VC9000DJ_VDEC 2 +#define JH8100_SWCLK_VC9000DJ_APB 3 +#define JH8100_SWCLK_VDEC_AXI 4 +#define JH8100_SWCLK_VC9000D_AXI 5 +#define JH8100_SWCLK_VC9000D_VDEC 6 +#define JH8100_SWCLK_VC9000D_APB 7 +#define JH8100_SWCLK_JPEG_ICG_EN 8 +#define JH8100_SWCLK_VDEC_ICG_EN 9 + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ */ diff --git a/include/dt-bindings/reset/starfive,jh8100-crg.h b/include/dt-bindings/reset/starfive,jh8100-crg.h index 30a99c78341a..de4f25dc301d 100644 --- a/include/dt-bindings/reset/starfive,jh8100-crg.h +++ b/include/dt-bindings/reset/starfive,jh8100-crg.h @@ -91,4 +91,12 @@ #define JH8100_NERST_SYS_IOMUX_E 48 #define JH8100_NERST_DUBHE_TVSENSOR 49 +/* + * SWCRG resets: assert0 + */ +#define JH8100_SWRST_PRESETN 0 +#define JH8100_SWRST_VC9000DJ 1 +#define JH8100_SWRST_VC9000D 2 +#define JH8100_SWRST_DDR_TVSENSOR 3 + #endif /* __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ */ -- 2.34.1
