Hi Lin-san, On Mon, Dec 25, 2023 at 10:37 AM Yu Chien Peter Lin <peterlin@xxxxxxxxxxxxx> wrote: > > Hi All, > > This patch series introduces the Andes PMU extension, which serves > the same purpose as Sscofpmf. To use FDT-based probing for hardware > support of the PMU extensions, we first convert T-Head's PMU to CPU > feature alternative, then add Andes PMU alternatives. > > Its non-standard local interrupt is assigned to bit 18 in the > custom S-mode local interrupt enable/pending registers (slie/slip), > while the interrupt cause is (256 + 18). > > Mainline OpenSBI has supported Andes PMU extension: > - https://github.com/riscv-software-src/opensbi/tree/master > Linux patches (based on v6.7-rc7) can be found on Andes Technology GitHub > - https://github.com/andestech/linux/commits/andes-pmu-support-v6 > > The PMU device tree node used on AX45MP: > - https://github.com/riscv-software-src/opensbi/blob/master/docs/pmu_support.md#example-3 > > Locus Wei-Han Chen (1): > riscv: andes: Support specifying symbolic firmware and hardware raw > events > > Yu Chien Peter Lin (15): > riscv: errata: Rename defines for Andes > irqchip/riscv-intc: Allow large non-standard interrupt number > irqchip/riscv-intc: Introduce Andes hart-level interrupt controller > dt-bindings: riscv: Add Andes interrupt controller compatible string > riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes > INTC > perf: RISC-V: Eliminate redundant interrupt enable/disable operations > RISC-V: Move T-Head PMU to CPU feature alternative framework > perf: RISC-V: Introduce Andes PMU for perf event sampling > dt-bindings: riscv: Add T-Head PMU extension description > dt-bindings: riscv: Add Andes PMU extension description > riscv: dts: allwinner: Add T-Head PMU extension for sun20i-d1s > riscv: dts: sophgo: Add T-Head PMU extension for cv1800b > riscv: dts: sophgo: Add T-Head PMU extension for sg2042 > riscv: dts: thead: Add T-Head PMU extension for th1520 > riscv: dts: renesas: Add Andes PMU extension for r9a07g043f > The above patches dont apply cleanly on top of below branches. Can you please rebase and re-send. https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/log/?h=fixes https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/log/?h=for-next https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/log/?h=renesas-dts-for-v6.8 Cheers, Prabhakar > .../devicetree/bindings/riscv/cpus.yaml | 6 +- > .../devicetree/bindings/riscv/extensions.yaml | 13 ++ > arch/riscv/Kconfig.errata | 13 -- > arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 2 +- > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 +- > arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 2 +- > arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 128 +++++++++--------- > arch/riscv/boot/dts/thead/th1520.dtsi | 8 +- > arch/riscv/errata/andes/errata.c | 10 +- > arch/riscv/errata/thead/errata.c | 19 --- > arch/riscv/include/asm/errata_list.h | 19 +-- > arch/riscv/include/asm/hwcap.h | 2 + > arch/riscv/include/asm/vendorid_list.h | 2 +- > arch/riscv/kernel/alternative.c | 2 +- > arch/riscv/kernel/cpufeature.c | 2 + > drivers/irqchip/irq-riscv-intc.c | 89 ++++++++++-- > drivers/perf/Kconfig | 27 ++++ > drivers/perf/riscv_pmu_sbi.c | 47 +++++-- > include/linux/soc/andes/irq.h | 18 +++ > .../arch/riscv/andes/ax45/firmware.json | 68 ++++++++++ > .../arch/riscv/andes/ax45/instructions.json | 127 +++++++++++++++++ > .../arch/riscv/andes/ax45/memory.json | 57 ++++++++ > .../arch/riscv/andes/ax45/microarch.json | 77 +++++++++++ > tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 + > 24 files changed, 592 insertions(+), 151 deletions(-) > create mode 100644 include/linux/soc/andes/irq.h > create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json > create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json > create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json > create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json > > -- > 2.34.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@xxxxxxxxxxxxxxxxxxx > http://lists.infradead.org/mailman/listinfo/linux-riscv
