This patchset adds the G4 tables and G4/G3 compatibles for X1E80100 platforms. Also adds the pciphy_v6_regs_layout to be used by the G4x2 phy and switches all the old QMP v6 PHYs to use the new regs layout. Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx> --- Changes in v2: - Added Krzysztof's R-b tag to first patch - Added new patch which brings the pciephy_v6_regs_layout and made sure all older (existing) QMP v6 are using that. - Switched the regs layout of the x1e80100 gen4x2 to the new pciephy_v6_regs_layout - Link to v1: https://lore.kernel.org/r/20231222-x1e80100-phy-pcie-v1-0-b74ac13390bf@xxxxxxxxxx --- Abel Vesa (3): dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHYs phy: qcom: qmp-pcie: Add QMP v6 registers layout phy: qcom-qmp-pcie: Add support for X1E80100 g3x2 and g4x2 PCIE .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 6 + drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 186 ++++++++++++++++++++- 2 files changed, 189 insertions(+), 3 deletions(-) --- base-commit: 8a9be2a3cb673dba9d22311beb74be261f0b3f15 change-id: 20231201-x1e80100-phy-pcie-ef74adb9af30 Best regards, -- Abel Vesa <abel.vesa@xxxxxxxxxx>
