On Fri, Dec 22, 2023 at 10:54 AM Peter Griffin <peter.griffin@xxxxxxxxxx> wrote:
>
> MCT has one global timer and 8 CPU local timers. The global timer
> can generate 4 interrupts, and each local timer can generate an
> interrupt making 12 interrupts in total.
>
> Signed-off-by: Peter Griffin <peter.griffin@xxxxxxxxxx>
> ---
Reviewed-by: Sam Protsenko <semen.protsenko@xxxxxxxxxx>
> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> index 9747cb3fa03a..4b09e740b58a 100644
> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> @@ -292,6 +292,26 @@ cmu_misc: clock-controller@10010000 {
> clock-names = "dout_cmu_misc_bus", "dout_cmu_misc_sss";
> };
>
> + timer@10050000 {
> + compatible = "google,gs101-mct",
> + "samsung,exynos4210-mct";
> + reg = <0x10050000 0x800>;
> + interrupts = <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&ext_24_5m>, <&cmu_misc CLK_GOUT_MISC_MCT_PCLK>;
> + clock-names = "fin_pll", "mct";
> + };
> +
> watchdog_cl0: watchdog@10060000 {
> compatible = "google,gs101-wdt";
> reg = <0x10060000 0x100>;
> --
> 2.43.0.472.g3155946c3a-goog
>
