Hi everyone, This series is an attempt to get feedback on decoding D1 efuse speed bins in the Sun50i H6 cpufreq driver, and turning the result into a meaningful value that selects voltage ranges in an OPP table. I want to make sure I get this right before sending in a v3 of the D1 cpufreq support series here https://lore.kernel.org/linux-sunxi/20231218110543.64044-1-fusibrandon13@xxxxxxxxx/T/#t which is currently stuck at https://lore.kernel.org/linux-sunxi/aad8302d-a015-44ee-ad11-1a4c6e00074c@xxxxxxxxxxxx/ Changes in v3: - Drop 'len' parameter and pointer in sunxi_cpufreq_data::efuse_xlate() prototype Changes in v2: - Make speed bin decoding generic in one patch and add D1 support in a separate patch - Fix OPP voltage ranges to avoid stability issues Brandon Cheo Fusi (3): cpufreq: sun50i: Refactor speed bin decoding cpufreq: sun50i: Add support for D1's speed bin decoding riscv: dts: allwinner: Fill in OPPs arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 19 +++- drivers/cpufreq/sun50i-cpufreq-nvmem.c | 89 +++++++++++++++---- 2 files changed, 87 insertions(+), 21 deletions(-) -- 2.30.2
