On Fri, Dec 15, 2023 at 06:06:10PM +0100, Alain Volmat wrote: > The stm32mp25 has only a single interrupt line used for both > events and errors. In order to cope with that, reorganise the > error handling code so that it can be called either from the > common handler (used in case of SoC having only a single IT line) > and the error handler for others. > The CR1 register also embeds a new FMP bit, necessary when running > at Fast Mode Plus frequency. This bit should be used instead of > the SYSCFG bit used on other platforms. > Add a new compatible to distinguish between the SoCs and two > boolean within the setup structure in order to know if the > platform has a single/multiple IT lines and if the FMP bit > within CR1 is available or not. > > Signed-off-by: Valentin Caron <valentin.caron@xxxxxxxxxxx> > Signed-off-by: Alain Volmat <alain.volmat@xxxxxxxxxxx> Applied to for-next, thanks!
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