On 21/12/2023 18:20, Swapnil Jakhade wrote: > Add register sequences for USXGMII(156.25MHz) + SGMII/QSGMII(100MHz) > multilink configuration. USXGMII uses PLL0 and SGMII/QSGMII uses PLL1. > > Signed-off-by: Swapnil Jakhade <sjakhade@xxxxxxxxxxx> Reviewed-by: Roger Quadros <rogerq@xxxxxxxxxx> -- cheers, -roger
